Hello all, i am facing a problem in adc10-bit of msp430f2132 the problem is
In adc10-bit module i done a configuration it is giving correct answer but in the timing theoretical is not matching with practical, for each conversion one clock cycle is missing on what step the clock is missing i do not know.
in page slau144j 538 and 540 it is clearly show, tsync + tsmple + tconvert takes time for one conversion
eg. for 4SHT internal ref 3.5 adc10clk = adc10osc, DIV = 0.
tsync = 0.5 clock cycle of adc10osc
tsample = 4 clock cycles of adc10osc
tconvert = 13 clock cycles of adc10osc
for 1 clock the time is 0.0000002 sec
if i add all clock i get 17.5 and time is 0.0000035 sec ( 3.5 micor sec), but i am getting 3.22micosec in digital oscilloscope if i count the clock 16.5 is showing 1 clock is missning, here adc10clk is get on when start conversion active it switch off when not needed.
to check adc10clk i configured adc10clk bit in ic according to data sheet msp430f21x2 SLAS578J – NOVEMBER 2007 – REVISED JANUARY 2012 pabe no 49.
please if any one knows about this inform me.