MSP432P401R: Why is this needed: FLCTL->BANK0_RDCTL = (FLCTL->BANK0_RDCTL & ~(FLCTL_BANK0_RDCTL_WAIT_MASK) | FLCTL_BANK0_RDCTL_WAIT_1);

Part Number:MSP432P401R

Hi

Below a copy of sample program from the book, Programmable Microcontrollers by Cem Unsalan, with a few added lines by me.

My questions is, why do we need to set the flash memory wait timing? I don't see that the program is doing anything with the flash memory?

I am reluctant to try commenting out those lines because I tried that once and the MSP432P401R bricked just about then. Correlation is not causation but it took a long time to un-brick and I am still not sure what parts of the many attempts were truly effective.

Thanks,

Chris

// Listing _7p7_A_main.c

#include "msp.h"
#define LED1 BIT0
#define RED BIT0
#define GREEN BIT1
#define BLUE BIT2

uint8_t p1_check, p2_Out, p2_check;

#define TIMER_PERIOD 300000

void main(void)
{
WDT_A->CTL = WDT_A_CTL_PW | WDT_A_CTL_HOLD; // stop watchdog timer

P1->DIR = LED1;
P2->DIR = RED | GREEN | BLUE;
P1->OUT = P2->OUT = p1_check = p2_check = 0;
p2_Out = 0;

TIMER32_1->CONTROL = TIMER32_CONTROL_SIZE | // T32CONTROL1 Bit 1 = 1, Select 32 bit counter
TIMER32_CONTROL_MODE | // T32CONTROL1 Bit 6 = 1, Timer in Periodic Mode
TIMER32_CONTROL_PRESCALE_1;// T32CONTROL1 Bit 2 = 2, Prescale = Divide by 16
TIMER32_1->LOAD = TIMER_PERIOD;

while(PCM->CTL1 & PCM_CTL1_PMR_BUSY) ;
PCM->CTL0 - PCM_CTL0_KEY_VAL | PCM_CTL0_AMR_1;
while(PCM->CTL1 & PCM_CTL1_PMR_BUSY) ;

FLCTL->BANK0_RDCTL = (FLCTL->BANK0_RDCTL & ~(FLCTL_BANK0_RDCTL_WAIT_MASK) | FLCTL_BANK0_RDCTL_WAIT_1); // Set FLCTL_BANK0_RDCTL bit 12
/*
FLCTL->BANK0_RDCTL = (FLCTL->BANK0_RDCTL & ~(FLCTL_BANK0_RDCTL_WAIT_MASK) // Reset FLCTL_BANK0_RDCTL bits 15-12
| FLCTL_BANK0_RDCTL_WAIT_1); // Set FLCTL_BANK0_RDCTL bit 12
*/
FLCTL->BANK1_RDCTL = (FLCTL->BANK1_RDCTL & ~(FLCTL_BANK1_RDCTL_WAIT_MASK) // Reset FLCTL_BANK1_RDCTL bits 15-12
| FLCTL_BANK1_RDCTL_WAIT_1); // Set FLCTL_BANK1_RDCTL bit 12

PJ->SEL0 |= BIT2 | BIT3;
PJ->SEL1 &= ~(BIT1 | BIT2);
CS->KEY = CS_KEY_VAL;
CS->CTL2 |- CS_CTL2_HFXT_EN | CS_CTL2_HFXTFREQ_6;
while(CS->IFG & CS_IFG_HFXTIFG)
CS->CLRIFG |= CS_CLRIFG_CLR_HFXTIFG;
CS->CTL1 &= ~(CS_CTL1_SELM_MASK | CS_CTL1_DIVM_MASK);
CS->CTL1 |= CS_CTL1_SELM_5;
CS->KEY = 0;

TIMER32_1->CONTROL |= TIMER32_CONTROL_ENABLE // T32CONTROL1 Bit 1 = 7, Enable Timer
| TIMER32_CONTROL_IE; // T32CONTROL1 Bit 1 = 5, Enable Timer Interrupt

__enable_irq();
NVIC->ISER[0] = 1 <<((T32_INT1_IRQn) & 31);

SCB->SCR |= SCB_SCR_SLEEPONEXIT_Msk;
__sleep();
}

void T32_INT1_IRQHandler(void)
{
TIMER32_1->INTCLR = 0; // Write anything to register T32INTCLR clears interrupt output
p1_check = P1->OUT;
P1->OUT ^=LED1;
p1_check = P1->OUT;
p2_check = ~(RED | GREEN | BLUE);
P2->OUT &= ~(RED | GREEN | BLUE);
p2_Out <<= 1;
if(!(0x7 & p2_Out))
p2_Out = RED;
P2->OUT |= p2_Out;
}