MSP430 ADC issue

I'm having a problem getting the ADC to perform conversions from a single input.

Steps taken:

1. Apply a high DC input voltage
2. Setup and enable ADC12  (see setting below)
3. Set ENC & ADC12SC bits
4. Wait for ADC12BUSY to go low
5. Wait for ADC12IFG0 to go high  (not interrupt driven)
6. Read ADC12MEM0  (first read)
7. Apply a low DC input voltage
8. Set ENC & ADC12SC bits
9. Wait for ADC12BUSY to go low
10. Wait for ADC12IFG0 to go high  (not interrupt driven)
11. Read ADC12MEM0 (last read)

The first-read is good, the last-read is wrong.  Is there something wrong with this approach?  (What am I missing?)

Here are my settings:

ADC12CTL0    0x0C72    ADC12 Control 0 [Memory Mapped]    
    SHT1    0000 - SHT1_0    ADC12 Sample Hold 0 Select 0    
    SHT0    1100 - SHT0_12    ADC12 Sample Hold 0 Select 0    
    MSC    0    ADC12 Multiple SampleConversion    
    REF2_5V    1    ADC12 Ref 0:1.5V / 1:2.5V    
    REFON    1    ADC12 Reference on    
    ADC12ON    1    ADC12 On/enable    
    ADC12OVIE    0    ADC12 Overflow interrupt enable    
    ADC12TOVIE    0    ADC12 Timer Overflow interrupt enable    
    ENC    1    ADC12 Enable Conversion    
    ADC12SC    0    ADC12 Start Conversion    
ADC12CTL1    0x0200    ADC12 Control 1 [Memory Mapped]    
    CSTARTADD    0000 - CSTARTADD_0    ADC12 Conversion Start Address 0    
    SHS    00 - SHS_0    ADC12 Sample/Hold Source 0    
    SHP    1    ADC12 Sample/Hold Pulse Mode    
    ISSH    0    ADC12 Invert Sample Hold Signal    
    ADC12DIV    000 - ADC12DIV_0    ADC12 Clock Divider Select 0    
    ADC12SSEL    00 - ADC12SSEL_0    ADC12 Clock Source Select 0    
    CONSEQ    00 - CONSEQ_0    ADC12 Conversion Sequence Select 0    
    ADC12BUSY    0    ADC12 Busy    
ADC12IFG    0x0000    ADC12 Interrupt Flag [Memory Mapped]    
ADC12IE    0x0000    ADC12 Interrupt Enable [Memory Mapped]    
ADC12IV    0x0000    ADC12 Interrupt Vector Word [Memory Mapped]    
ADC12MEM0    0x0A67    ADC12 Conversion Memory 0 [Memory Mapped]    
ADC12MCTL0    0x54    ADC12 Memory Control 0 [Memory Mapped]    
    EOS    0    ADC12 End of Sequence    
    SREF    101 - SREF_5    ADC12 Select Reference Bit 0    
    INCH    0100 - INCH_4    ADC12 Input Channel Select Bit 0