*** MSP432 Driverlib Demos all 3Mhz -- problems with 48Mhz, SMCLK, and I2C ***

I have been using the MSP432 at a clients request for a couple months. Initially, I got everything I needed to work based on the examples (ADC, timers, interrupts, UART, and SPI) -- but didn't need to I2C, so left it for another day.

Now, I need the I2C and the examples all run at 3MHZ in the system_msp432p401r.c so I change the 3000000 to 48000000 in the file, and the conditional compilation should take care of the rest (I am using the vanilla system_msp432p401r.c file). 

My problem is that the demos all run in 3Mhz mode, so when you pump the processor to 48Mhz, everything breaks on I2C, I set the config up correctly as below:

// I2C master configuration for EUSCI_B @ 100Khz
const eUSCI_I2C_MasterConfig i2cConfig100Khz =
{
        EUSCI_B_I2C_CLOCKSOURCE_SMCLK,          // SMCLK Clock Source
	48000000,                                                                    // SMCLK = ??
        EUSCI_B_I2C_SET_DATA_RATE_100KBPS,      // Desired I2C Clock of 100khz
        0,                                                                                     // No byte counter threshold
        EUSCI_B_I2C_NO_AUTO_STOP                             // No Autostop
};


// I2C master configuration for EUSCI_B @ 400Khz
const eUSCI_I2C_MasterConfig i2cConfig400Khz =
{
        EUSCI_B_I2C_CLOCKSOURCE_SMCLK,          // SMCLK Clock Source
	48000000,                                                                    // SMCLK = ??
        EUSCI_B_I2C_SET_DATA_RATE_400KBPS,      // Desired I2C Clock of 400khz
        0,                                                                                    // No byte counter threshold
        EUSCI_B_I2C_NO_AUTO_STOP                          // No Autostop
};

I run the demo and it doesn't work anymore properly.

Now, I have read in the data sheet that the SMCLK as the source for the I2C has a max of 12/24 MHZ depending on the vcore. That's great, but I am not sure how to decrease the SMCLK divider without resorting to looking up dividers, PLL settings etc. Usually, there is a clock setting tool from most ARM vendors, that you make changes and then plug the output code into the analogous system_msp432p401r.c file, but there is no such tool with MSP432.

So, I have everything working at 3Mhz, and I can even get things working at 12Mhz for the system_clock by fudging the values in the above config, but what I really need to do is SET SMCLK divider, so that its 12/24Mhz when the system_clock is 48Mhz.

If anyone has dealt with this, did you solve it and am I missing something? Is there a tool or easier way to set these clock dividers?

I am not sure why the author Thomas of the demos ran everything at 3Mhz for I2C especially, since it would be nice to see HOW to make the changes and consider the importance of the SMCLK constraint to 12/24Mhz -- seems like the demos avoided this issue and didn't deal with them by running SLOW.

I have spent too many hours trying to figure this out, client is about to punt on MSP432 and pick ST, Freescale, or Atmel, so I really need a clear solution to this and how best to set clocks in a safe way, especially the SMCLK -- I would have thought the system_msp432... file would do this, but as I look at the code, I see no mention of SMCLK, just voltages, the flash wait states, and a few other things, but there are no "smarts" in the code to deal withe SMCLK and setting it correctly.

Alas, what is SMCLK set to by the default system_msp432p401r file? Does it change with changing the system_clock speed? If so, where?

Bottom line, I have I2C working slow, I just need to know what I need to do to address 48Mhz and SMCLK as the clock source for I2C which has a limit of 12/24 mhz.

Help!

Thanks,

Andre'