SPI clock generation on MSP430FR5969 MCU

Hi all,

I'm using 3 wires mode SPI (eUSCI peripheral in SPI mode) and trying to receive 20 bytes of data from the slave (my slave doesn't support Slave Select).

It seems that I should write SPI TX buffer on master side 21 times (for example command_byte 0x00 0x00 ... 0x00) in order to receive the data (writing a data to Tx buffer on master side is mandatory in order to trigger (generate) 8 SCK cycles). I guess this is because Tx and Rx buffers (and shift registers) are separated on MSP430fr5969 side. Am I right?

Thanks in advance,

Stevan