MSP430F6659 DCO ISSUE

i am working on MSP430F6659

here in ucs system my code is 

int main(void) {
WDTCTL = WDTPW | WDTHOLD; // Stop watchdog timer

UCSCTL0_H |= 0b00011111;
UCSCTL0_L &= 0b00000000;
UCSCTL1 |= DCORSEL_7;
UCSCTL4 |= SELS_4;

__delay_cycles(100000);

P3DIR |= BIT4;
P3SEL |= BIT4;

}

my question is how to get maximum clk frequency = 135mhz.

when i am compiling above code on ccs6 it shows all DCO bits are 0 and all the MOD bits are 1. What should i do?