Set XT1 clock on MSP430F5659 > ucs_clockinit () issue

Dear All,

I'm building a board based on MSP430F5659.

Now, I'm trying to set the main system clock, sourcing from the X1 Crystal 32KHz.

So, I had my code running on the MSP430F5529LP, but I got issue when ported to MSP430F5659: the code is not able to set the X1 clock.

As follows a copy/paste of the ucs_clockinit() function from the clockinit.c file.

my questions:

1- Have I missed something ?

2- on The MSP430F5529, we use the P5SEL to enable the X1. for the MSP430F5659, I beleive it 's not required view that the X1 pinout (XIN=pin 13 and XOUT=14) are not shared with I/O function. 

Thanks.

uint16_t ucs_clockinit(unsigned long freq, uint16_t use_xt1, uint16_t vlo_as_aclk)
{
	unsigned long attempts = 0; //, divided;
	uint16_t flld;
	static uint16_t did_vcoreup = 0;

	UCSCTL4 = SELM__DCOCLK | SELS__DCOCLK;
	if (vlo_as_aclk)
		UCSCTL4 = (UCSCTL4 & ~SELA_7) | SELA__VLOCLK;

	if (use_xt1) {

		#ifdef __MSP430F5172
		PJSEL |= BIT4|BIT5;
		#endif
		#ifdef __MSP430F5529
		P5SEL |= BIT4|BIT5;
		#endif

		UCSCTL6 &= ~XT1OFF;
		UCSCTL6 = (UCSCTL6 & ~(XCAP_3|XT1DRIVE_3)) | XCAP_0 | XT1DRIVE_3;
		if (!vlo_as_aclk)
			UCSCTL4 = (UCSCTL4 & ~SELA_7) | SELA__XT1CLK;
		// Wait for XT1 to stabilize
		do {
			UCSCTL7 &= ~XT1LFOFFG;
			attempts++;
		} while (UCSCTL7 & XT1LFOFFG && attempts < 1000000);
		if (attempts == 1000000)
			return 0;  // XT1 FAILED,  >>> My code stops here <<<<<


		UCSCTL3 = SELREF__XT1CLK;
	} else {
		UCSCTL6 |= XT1OFF;
		#ifdef XT1HFOFFG
		UCSCTL7 &= ~(XT1LFOFFG | XT1HFOFFG);
		#else
		UCSCTL7 &= ~XT1LFOFFG;
		#endif
		UCSCTL3 = SELREF__REFOCLK;
	}

	// Using frequency, determine which VCore level we should achieve.
	// Set Vcore to maximum
	if (!did_vcoreup) {
		SetVCoreUp(1);
		SetVCoreUp(2);
		SetVCoreUp(3);
		did_vcoreup = 1;
	}

	// Initialize DCO
	__bis_SR_register(SCG0);  // Disable FLL control loop
	UCSCTL0 = 0x0000;

	// Determine which DCORSEL we should use
	UCSCTL1 = _dcorsel_compute_f5172(freq);

	// FLL reference is 32768Hz, determine multiplier
	flld = _flld_compute(freq);
	UCSCTL2 = ((flld/2) << 12) | (uint16_t)(freq / 32768UL / flld);

	__bic_SR_register(SCG0);  // Re-enable FLL control loop

	// Loop until XT1 & DCO fault flags have cleared
	do {
		#ifdef XT1HFOFFG
		UCSCTL7 &= ~(XT1LFOFFG | XT1HFOFFG | DCOFFG);
		#else
		UCSCTL7 &= ~(XT1LFOFFG | DCOFFG);
		#endif
		SFRIFG1 &= ~OFIFG;
	} while (SFRIFG1 & OFIFG);

	// DCOCLK stable
	return 1;
}