Part Number:MSP432E401Y
The project implements an MSP432E401Y, a 3.3V buck regulator, and POE Ethernet jack as the core.
~WAKE is tied to ground and ~HIB is left floating, per Design Guidelines (slaa770, 4.15).
This particular board has never had firmware loaded yet.
When connected to a POE-capable switch, the switch's POE Good LED lights, and the Link LED comes on; Vdd measures 3.2+ VDC.
After a short time (< a minute?), Link LED goes out, and we see Vdd has dropped below 3 VDC.
This was first observed when the debugger probe was attached, but later found to be the case, without the debugger.
Is there a weird mode, possibly drawing significantly more current than expected, that the uP may enter on start-up?
Next step will be to supply a solid 3.3V, bypassing POE, while waiting for any input from the Community.
Thank you!
Dave