MSP430F5438A PWM TB0 chan2

I have an application generating multiple PWM outputs that works perfectly on a MSP430F5438 eval board. On a custom board with MSP430F5438A, some of the PWM channels aren't working right.

Initialization code includes:

// timer B0 = SMCLK(8.192MHz), 12 bit length, continuous mode,
// interrupt on TBIFG
TB0CTL = CNTL_1 + TBSSEL_2 + MC_2 + TBCLR + TBIE;
// TB0 counter 0 = interrupt on compare CCIFG
TB0CCTL0 = CCIE;

PWM duty cycle is set via TB0CCR1, TB0CCR2, etc.

At TBIV interrupt (2KHz), handler code includes:

	// all PWM outputs high
	TB0CCTL1 = OUTMOD_0 + 4;
	TB0CCTL2 = OUTMOD_0 + 4;

	// reset on count reached
	TB0CCTL1 = OUTMOD_5;
        TB0CCTL2 = OUTMOD_5;

So on the eval board, TB0 chan 1 and 2 work as expected (per scope trace). On the custom board, chan 1 is fine but chan 2 is always a very short duty cycle. If I move the "TB0CCTL2 = OUTMOD_5;" later in the ISR, the duty cycle is longer, so it appears that this immediately resets the output. If I disable that statement, the output is always high - so I think the hardware connections are ok. I can read back the correct limit count in TB0CCR2, and verified that TBCLGRP0 and CLLD are zero so there shouldn't be any group or delayed update of the latched limit TB0CL2 (which unfortunately can't be read). Nothing in the MSP430F5438A errata seems to apply.

Any suggestions?