Part Number:MSP430F248
Hello,
Is a NOP required between a EINT instruction and BIS.W #0x00d0,SR (enter LPM3) and a RET?
This is the code:
C390 861E BIC.W #1,Timer_B7_TBCCTL4
D0B0 0010 8618 BIS.W #0x0010,Timer_B7_TBCCTL4
D232 EINT
D032 00D0 BIS.W #0x00d0,SR
4130 RET
EINT and BIS.W 0xD0,SR act both on register SR, there are a few posts on e2e that discuss the topic of a NOP after modifying LPM bits in the SR register (or EINT/DINT btw: https://e2e.ti.com/support/microcontrollers/msp430/f/166/p/53319/838507#pi316701filter=all&pi316701scroll=false)
The F248 has the bug CPU19 (unintentional register read after CPUOFF bit modification) and it also lists RET which is a MOV @SP+,PC (correct? please confirm), would that increment the SP register twice?
This code was generated form assembly using IAR workbench, so if there's a nop required I'd have to do it in assembly for every occurrence.
This project suffers from unexpected resets (data/timing dependant, not easily reproduced).
It is not the watchdog irq: the WDT vector 0xfff4 was redirected to 0xff00 which now contains 0x3fff (jmp to self, deadloop) and the WDTNMI bit is 0 (==wdt triggers irq not reset).
After the unintentional reset I can catch the pc upon re-entry @4008 and look at the stack:
SP is @20F0
0x20F0: FFFF 5FE2 0000 0420 55AA 00DC 54EE 402C
4028: 12B0 5000 CALL #0x5000 ; next pc 0x402c
55a6: 12B0 5F6C CALL #0x5f6c ; next pc 0x55aa
5f6c: 1204 PUSH R4 ; on stack
5f6e: 1205 PUSH R5 ; on stack
Interrupt, pushes PC, SR:
PC @ 5fe2
SR = FFFF ?
What happens if the upper bits in SR are set?
Best regards,
Lo
