Tool/software:
Hi TI support,
We're super tight on board space and so only critical parts are making the cut for this board design, but we still need solid performance. My question is about the Note B from Figure 6-4 on the M430FR5989SRGCREP datasheet, page 138. It says the following:
"The device RST/NMI/SBWTDIO pin is used in 2-wire mode for bidirectional communication with the device during
JTAG access, and any capacitance that is attached to this signal may affect the ability to establish a connection with
the device. The upper limit for C1 is 2.2 nF when using current TI tools."
We are using SBW for production programming and dev debugging, and therefore not using the Reset behavior, since that pin will be used for SBW. Given the above note saying "any capacitance ... may affect" reliable SBW connection, is it better to NOT have ANY pull down capacitor on that RST pin? Or is one still required?
If still required, then what's a safe, conservative value. It says not more than 2.2nF, so would 1nF be good? Need your design input on this please. And ideally, if it's better to not have any cap at all, then that would save us on board space, which is great. Thoughts?
Thanks,
Brian
