msp432 clock sources and signals

For UART is important to first define what clk source are we going to use, in CS->CTL1 register ACLK(auxiliary clock), SMCLK(low speed subsystem master clock), MCLK(master clock) and BCLK(Low speed backup domain clock) sources are chosen, but what are they for??, and under what criterion I chose their oscilators. In this case (code), In this case (code), why  for a DCO of 12MHz use REFOCLK for ACLK, DCOCLK for SMCLK and MCLK.

UART example for 9600 bauds transmission.

CS->KEY = 0x695A;                        // Unlock CS module for register access
  CS->CTL0 = 0;                            // Reset tuning parameters
  CS->CTL0 = CS_CTL0_DCORSEL_3;                   // Set DCO to 12MHz (nominal, center of 8-16MHz range)
                                         // Select ACLK = REFO, SMCLK = MCLK = DCO
  CS->CTL1 = CS_CTL1_SELA_2 | CS_CTL1_SELS_3 | CS_CTL1_SELM_3;
  CS->KEY = 0;