Part Number:MSP430FR5969
Environment: IAR for MSP430 (full version) - debugging code on Launchpad MSP-EXP430FR5969
Hardware configuration: DCO = 16MHz, 0 wait states on FRAM (also experimented changing this to no effect)
Simple task: Toggle a GPIO pin as fast as possible
Emitted assembler from IAR:
??tleReadFactory_0:
XOR.B #0x80, &0x202
JMP ??tleReadFactory_0
This should take 8 instruction cycles - 5 for the xor and 3 for the jmp - verified with the cycle counter on the EEM
When I look at the pin with a scope, the pin toggles every 1usec - exactly twice the expected interval of (1/16MHz)*8 = 500usec
It isn't FRAM wait states as I tried changing them which confirms that I am probably at 100% on the cache hits which makes sense given it is just a tiny little loop
Verified the DCO via SMCLK with 2 prescale and output to a pin. changing the DCO changes the interval as expected with the factor of 2 conserved.
Looking for ideas of where else to look for the timing leak. Does the embedded emulation add that much overhead?