Part Number:MSP430FR4133
I'm trying to interface the MSP430 launchpad with AFE4300 evaluation board to establish spi communication. I know my hardware connections are right, as with the same connections, I can read and write to the registers in the AFE from the provided gui for AFE4300 which also uses spi.
Below is my code. The code attempts to write 0x0408 to 0x0A register and then read the value at that address. I probe the signals at MISO, MOSI, SCLK and STE (P5.0) using an oscilloscope. The issue is only with MISO. MISO goes high as STE is made low. It goes back to zero when MSP430 begins to transmit. It stays low until next time, when STE is made low. I checked the status flags. I would get overrun error. To correct that, I added this line of code inside my ISR (saw someone using it in some forum), "while (UCB0STAT & UCBUSY);". My transmit buffer takes the right values and transmits correctly, but I always read a zero. Kindly help me with my issue. I would have used eUSCI_A0 instead of eUSCI_B0 to verify, but the launchpad for MSP430 has a reset button at P1.2 and a red LED at P1.0.
#include <msp430.h>
unsigned char RXData =0;
unsigned char TXData;
int main(void)
{
WDTCTL = WDTPW | WDTHOLD; // Stop watchdog timer
P5SEL0 |= BIT1 | BIT2 | BIT3; // set 3-SPI pin as second function
UCB0CTLW0 |= UCSWRST; // **Put state machine in reset**
// 4-pin, 8-bit SPI master
UCB0CTLW0 |= UCMST|UCSYNC|UCCKPH|UCMSB|UCMODE_1|UCSTEM;
// Clock polarity high, MSB
UCB0CTLW0 |= UCSSEL__SMCLK; // Select SMCLK
UCB0BR0 = 0x04; // /2,fBitClock = fBRCLK/(UCBRx+1). Time period of SCLK is 4us
UCB0BR1 = 0;
//UCA0MCTLW = 0; // No modulation
UCB0CTLW0 &= ~UCSWRST; // **Initialize USCI state machine**
PM5CTL0 &= ~LOCKLPM5; // Disable the GPIO power-on default high-impedance mode to activate previously configured port settings
P5DIR |= BIT0; //chip select
// Writing 0x0408 to 0x0A register
P5OUT &= ~BIT0; //chip select low
TXData = 0x0A; // Select address to transmit
UCB0IE |= UCTXIE; // Enable TX interrupt
__bis_SR_register(GIE); // Enable interrupts
__delay_cycles(100); // Delay before next transmission
TXData = 0x04; // Select MSB to transmit
UCB0IE |= UCTXIE; // Enable TX interrupt
__bis_SR_register(GIE); // Enable interrupts
__delay_cycles(100);
TXData = 0x08; // Transmit LSB
UCB0IE |= UCTXIE; // Enable TX interrupt
__bis_SR_register(GIE);// Enable interrupts
__delay_cycles(100); // Delay before next transmission
P5OUT |= BIT0; //chip select high
__delay_cycles(100);
//Reading from the same register
P5OUT &= ~BIT0; //Chip select low
//Send TXdata into the buffer
TXData = (0x20 | 0x0A); // Holds Address with read bit enabled
UCB0IE |= UCTXIE; // Enable TX interrupt
__bis_SR_register(GIE); // Enable interrupts
__delay_cycles(100); // Delay before next transmission
UCB0IE |= UCRXIE; // Enable USCI_B0 RX interrupt
__bis_SR_register(GIE); // Enable interrupts
TXData = 0x00; // Transmit dummy data
UCB0IE |= UCTXIE; // Enable TX interrupt
__bis_SR_register(GIE); // Enable interrupts
__delay_cycles(100); // Delay before next transmission
//Receive MSB
UCB0IE |= UCRXIE; // Enable USCI_B0 RX interrupt
__bis_SR_register(GIE); // Enable interrupts
TXData = 0x00; // Transmit dummy data
UCB0IE |= UCTXIE; // Enable TX interrupt
__bis_SR_register(GIE); // Enable interrupts
__delay_cycles(100); // Delay before next transmission
//Receive LSB
UCB0IE |= UCRXIE; // Enable USCI_B0 RX interrupt
__bis_SR_register(GIE); // Enable interrupts
//Chip select high
P5OUT |= BIT0;
__delay_cycles(100);
}
#if defined(__TI_COMPILER_VERSION__) || defined(__IAR_SYSTEMS_ICC__)
#pragma vector=USCI_B0_VECTOR
__interrupt void USCI_B0_ISR(void)
#elif defined(__GNUC__)
void __attribute__ ((interrupt(USCI_B0_VECTOR))) USCI_B0_ISR (void)
#else
#error Compiler not supported!
#endif
{
switch(__even_in_range(UCB0IV,USCI_SPI_UCTXIFG))
{
case USCI_NONE: break; // Vector 0 - no interrupt
case USCI_SPI_UCRXIFG:
while (UCB0STAT & UCBUSY);
RXData = UCB0RXBUF;
UCB0IFG &= ~UCRXIFG;
break;
case USCI_SPI_UCTXIFG:
UCB0TXBUF = TXData; // Transmit characters
UCB0IE &= ~UCTXIE;
break;
default: break;
}
}