Part Number:msp430F5418A
Hi all,
I've been writing some MSP430 code to write some code to init clock and timers. I am using MSP430F5418A.
Here's my code snippet for clock. Here, I've set FLLD bits so that DCOCLKDIV = DCOCLK/2. By default, SMCLK = DCOCLKDIV since I don't change it at all.
void clock_init()
{
WDTCTL = WDTPW+WDTHOLD; // Stop WDT
SetVcoreUp (PMMCOREV_3); // Set VCore = 1.9V for 25MHz clock
P1DIR |= BIT0; // P1.0 output
P11DIR |= 0x07; // ACLK, MCLK, SMCLK set out to pins
P11SEL |= 0x07; // P11.0,1,2 for debugging purposes.
UCSCTL3 |= SELREF_2; // Set DCO FLL reference = REFO
UCSCTL4 |= SELA_2; // Set ACLK = REFO
__bis_SR_register(SCG0); // Disable the FLL control loop
UCSCTL0 = 0x0000; // Set lowest possible DCOx, MODx
UCSCTL1 = DCORSEL_6; // Select DCO range 24MHz operation
//*****FLLD_1 for dcoclockdiv = dcoclock/2*****//
UCSCTL2 = FLLD_1 + 731; // Set DCO Multiplier for 24MHz
// (N + 1) * FLLRef = Fdco
// (731 + 1) * 32768 = 24MHz
// Set FLL Div = fDCOCLK/2
__bic_SR_register(SCG0); // Enable the FLL control loop
// Worst-case settling time for the DCO when the DCO range bits have been
// changed is n x 32 x 32 x f_MCLK / f_FLL_reference. See UCS chapter in 5xx
// UG for optimization.
// 32 x 32 x 25 MHz / 32,768 Hz = 819200 = MCLK cycles for DCO to settle. We add some more time
__delay_cycles(500000);
__delay_cycles(500000);
// Loop until XT1,XT2 & DCO fault flag is cleared
do
{
UCSCTL7 &= ~(XT2OFFG + XT1LFOFFG + XT1HFOFFG + DCOFFG);
// Clear XT2,XT1,DCO fault flags
SFRIFG1 &= ~OFIFG; // Clear fault flags
}while (SFRIFG1&OFIFG); // Test oscillator fault flag
}
Now, in timer init, I've set up like this. The clock to timer module is given by SMCLK by setting TASSEL bits. So timer clock should be DCOCLKDIV = DCOCLK/2, right?
void timer_init()
{
//---------------------- TIMER A1 ---------------------------------//
TA1CCTL0 = CCIE; // CCR0 interrupt enabled //this sets global timer interrupt
TA1CCR0 = 766; // PWM Period(~32us) //31khz interval
TA1CCTL1 = OUTMOD_7; //reset/set
TA1CCTL2 = OUTMOD_7; //reset/set
TA1CCR1 = 0; //TA1.1
TA1CCR2 = 0; //TA1.2
TA1CTL = TASSEL_2 + MC_1 + TACLR; // SMCLK, upmode, clear TAR
}
However, it looks as if I am getting timer clk = DCOCLK = 2 * DCOCLKDIV since my timer interrupt gets fired accordingly. What am I missing?
Thanks in advance.