Part Number:MSP430FR2532
Hello,
I have some problems to configure the eUSCI with the correct settings and the right clock settings/deviders. First I think the hardware is okay. There are some bus participans wokring on Atmel processors and some bought ones. Between the RS485 IC and the MSP430 the scope shows me valid Data (analog scope, not data logger). For this reason I think I only fail with the right software settings. ;-)
I'm using IAR Embedded Workbench IDE 6.50.5.
I tried to remix some code examples: https://github.com/j-windsor/MSP430-DMX512/blob/master/main.c
The one from your example: msp430fr243x_euscia0_uart_01.c www.ti.com/.../slac700
The actual one of my try:
//#include "io430.h"
#include "msp430fr2532.h"
#define CHAN_1 BIT4 //PORT1 //OUTPUT 1
#define CHAN_2 BIT1 //PORT1 //OUTPUT 2
#define CHAN_3 BIT5 //PORT1 //OUTPUT 3
#define CHAN_4 BIT2 //PORT1 //OUTPUT 4
#define RX BIT5 //PORT2 //RX UART
#define TX BIT6 //PORT2 //TX UART
#define DE BIT7 //PORT2 //transmit enable UART
#define RE BIT1 //PORT3 //_receive enable UART (inverted)
//DMX512/RS485 Setup
unsigned int actChannel = 0; //variable for actual receiving byte
unsigned char busAddress = 0; //DMX Adress + 1
unsigned char rxData = 0; //value of received byte
//unsigned char byteReceived = 0; //byte received yet?
int main( void )
{
// Stop watchdog timer to prevent time out reset
WDTCTL = WDTPW + WDTHOLD;
P1SEL0 = 0x00;
P1SEL1 = 0x00;
P1DIR = CHAN_1 + CHAN_2 + CHAN_3 + CHAN_4; //chan1 and chan3 works
P1OUT = 0x00;//CHAN_1 + CHAN_2 + CHAN_3 + CHAN_4;
P2SEL0 = RX;
P2SEL1 = RX;
P2DIR = DE; //and ~RX
P2OUT = 0x00;
P3SEL0 = 0x00;
P3SEL1 = 0x00;
P3DIR = RE;
P3OUT = 0x00;
PM5CTL0 &= ~(LOCKLPM5);
//set oscillators:
__bis_SR_register(SCG0); // disable FLL
CSCTL3 |= SELREF__REFOCLK; // Set REFO as FLL reference source
CSCTL0 = 0; // clear DCO and MOD registers
CSCTL1 &= ~(DCORSEL_7); // Clear DCO frequency select bits first
CSCTL1 |= DCORSEL_3; // Set DCO = 8MHz
CSCTL2 = FLLD_0 + 243; // DCODIV = 8MHz
__delay_cycles(3);
__bic_SR_register(SCG0); // enable FLL
while(CSCTL7 & (FLLUNLOCK0 | FLLUNLOCK1)); // Poll until FLL is locked
CSCTL4 = SELMS__DCOCLKDIV | SELA__REFOCLK; // set default REFO(~32768Hz) as ACLK source, ACLK = 32768Hz
// default DCODIV as MCLK and SMCLK source
UCA1CTL1 |= UCSWRST; //pause for init
UCA1CTL1 |= UCSSEL1; //small clock, no error detection, no parity
UCA1CTL0 = UCSPB | UCMODE_1; //two low stop bits
//UCA1CTLW0 =
UCA1BR0 = 32; //250kBaud => 8.000.000 / 250.000 = 32
UCA1BR1 = 0;
UCA1CTLW0 &= ~UCSWRST; //restart after init
UCA1IE |= UCRXIE; //interrupt on receive
_BIS_SR(GIE); //interrupt enable
while(1)
{
if(UCA1STATW & UCBRK)
{
actChannel = 0; //reset channel counter
}
/*P1OUT = CHAN_1 + CHAN_2 + CHAN_3 + CHAN_4;
for(int i=0; i< 30000; i++);
P1OUT = 0x00;
for(int i=0; i< 30000; i++); */
}
}
#if defined(__TI_COMPILER_VERSION__) || defined(__IAR_SYSTEMS_ICC__)
#pragma vector=USCI_A1_VECTOR
__interrupt void USCI_A1_ISR(void)
#elif defined(__GNUC__)
void __attribute__ ((interrupt(USCI_A1_VECTOR))) USCI_A1_ISR (void)
#else
#error Compiler not supported!
#endif
{
switch(__even_in_range(UCA1IV,USCI_UART_UCTXCPTIFG))
{
case 0x02: //receive
rxData = UCA1RXBUF;
//byteReceived = 1;
if(actChannel == 2){
if(rxData > 127)
{
P1OUT |= CHAN_1;
}
else
{
P1OUT &= ~CHAN_1;
}
}
actChannel++; //increment channel
break;
default: break;
}
UCA1IFG &= ~UCTXIFG; //clear flag
}
I am a little bit confused with all the settings of the eUSCI. On page 575 of the Family/Users Guide there are some correction/modulation patterns. I just thought I can set the Clock to 8MHz and devide it down to 250 kBaud. The datasheet makes differences on page 576, if you will need a devider of more or less than 16. The example in slac700 is only for 9600 Baud and need all the corrections, right?
I would be very pleased if anyone has additional information or hints for me! :) I hope I pasted all important information.
Yours, Carsten