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MSP430F5359: Change of behavior: Comparator B interrupts don't self-clear?

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Part Number:MSP430F5359

We're migrating a design from using MSP430F2618 microprocessors to using MSP430F5359 microprocessors.

For the Comparator peripherals, the Comparator A+ documentation in the MSP430x2xx Family User's Guide, Literature Number: SLAU144J December 2004–Revised July 2013, the documentation clearly states that the Comparator A+ interrupts are self-clearing after they are processed. It both states this in the text and shows this in the interrupt logic diagram:

By comparison, the documentation for the Comparator B peripheral as documented in the MSP430x5xx and MSP430x6xx Family User's Guide, Literature Number: SLAU208P June 2008–Revised October 2016 is silent on the exact issue of whether interrupts are self-clearing:

As it turns out, they aren't self-clearing and we wasted some time discovering this fact.  If one reads between the lines, I suppose one could read the highlighted sentence to mean "An interrupt request will continue to be generated so long as GIE is set and either CBIE and CBIFG or CBIIE and CBIIFG are both set", but that certainly didn't jump out at me, being familiar as I was with the Comparator A+ behavior.

Specific testing confirms this "non-self clearing behavior" of the CBIFG and CBIIFG flags.

A question and a request:

1. Can you please confirm for the record that my understanding is correct and that this is an intended difference in behavior between the older Comparator A+ and the newer Comparator B?

2. If this is the intended behavior, could the documentation please be improved to explicitly state this behavior? Given the more-complex interrupt architecture of the Comparator B peripheral, it would also be really nice to create a logic diagram as was shown with Comparator A+. This would show the lack of a reset to the IRQ flop and would also show the logic that handles the twinned CBIE+CBIFG and CBIIE+CBIIFG "setters" along with the CBIES bit that can invert their effects.


MSP-EXP432P4111: SPI Configuration

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Part Number:MSP-EXP432P4111

Hello,

I have a spi configuration code which is written for a msp430 and DAC161S997. But i am trying to use it on my msp-exp432p4111. I think the problem is UCB0BR0 register. The register that i found(BRW) has different use.

msp430 code

	UCB0CTL1 |= UCSWRST;                                                       // Enable SW reset
	UCB0CTL0 |= (UCMST + UCMSB + UCSYNC + UCCKPH);                             // SPI Master, 3 wire, synchronous mode
	UCB0CTL1 |=  UCSSEL_2;                                                     //SMCLK
	UCB0BR0 = 8;                                                               // SMCLK/8 = SCLK (1MHz)
	UCB0BR1 = 0;
	UCB0CTL1 &= ~UCSWRST;                                                      // Clear SW reset, resume operation

the code i have made

	EUSCI_B0->CTLW0 |= EUSCI_B_CTLW0_SWRST;                                                       // Enable SW reset
	EUSCI_B0->CTLW0 |= (EUSCI_B_CTLW0_MST + EUSCI_B_CTLW0_MSB + EUSCI_B_CTLW0_SYNC + EUSCI_B_CTLW0_CKPH + EUSCI_B_CTLW0_UCSSEL_2);     // SPI Master, 3 wire, synchronous mode
        EUSCI_B_CMSIS(EUSCI_B0_BASE)->BRW = 48000000 / 1000000;
	EUSCI_B0->CTLW0 &= ~EUSCI_B_CTLW0_SWRST;                                              // Clear SW reset, resume operation

MSP430FR2522: Adhesive materials for CapTIvate MCUs

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Part Number:MSP430FR2522

Hi there!

I knows this might be a bit off-topic, but still is unavoidable part of CapTIvate technology.


I've seen that Design Guide mentions 3M 467MP and 468MP adhesives. I wonder what are other type of materials suitable as adhesives for capacitive-sensing? Are there any specific requirements regarding applying the adhesives to FR4 PCBs and/or overlay material?

Specifically, I'm interested in FR4 copper electrode to glass (~4mm) stackup. Any guidance is appreciated.

MSP430F6736A: Time spend in production to delete the Boot Strap Loader...

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Part Number:MSP430F6736A

Hi MSP team.

The BSL is deleted before programming the flash which takes an additional 5 seconds of programming time.

Is it possible to buy the MSP430F6736A without the Boot Strap Loader preprogrammed into flash?

BR

Anders Lange

CCS/EZ430-RF2500-SEH: ED demo code doesn't work (no connection)

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Part Number:EZ430-RF2500-SEH

Tool/software: Code Composer Studio

I am using the dev kit and I a demo code for the ED and AP. While AP sems to be correct (the red bubble flashes), there is sth wrong with the ED. After start, it should search for a connenction for a while, blinking leds. It doesn't, all it does is just quick blink just after launch. I think I tried everything - I comment out the line SMPL_Ioctl to use the addreses stored in config files. Before the removal (with random addreses) it also didn't work... It should work out of the box but it doesn't
My source https://e2e.ti.com/support/wireless-connectivity/sub-1-ghz/f/156/t/295876#

MSP432P401R: USB device not recognized when plugging in the launchpad

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Part Number:MSP432P401R

Support,

I am using the MSP432P401, new out of the box.  I plug it into USB and I get 'USB device not recognized'.  

I tried to update the driver but had no luck.  It says "your driver is already the latest".  The driver i pointed to was from C:\ti\ccsv8\ccs_base\emulation\windows\xds110_drivers\x64

Regards,

Marc

MSP432E401Y: Out-of_box demo: Could a 40-char Exosite 'token' fit into a uint32?

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Part Number:MSP432E401Y

Have recently been experimenting with the Out-of_box demo on this board. Among other things, have been trying to experimenting with re-provisioning, changing tokens, etc.

Noticing that the terminal interface command in this firmware does not accept a full - 40-char - length token as copied from Exosite. Interface is now repeating: 

Copy a temporary token from Exosite server to the LaunchPad using the command "Token".

Granted, I've got a bit more searching though source code to do, but, could the 40-char token fit into this (uint32_t) CIK size?

SaveCIKEEPROM(char *pcProvBuf)

    uint32_t ui32Len;

Fully willing to accept I've just got it all wrong. Please enlighten!

MSP432P401R: Timer A control and functionality

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Part Number:MSP432P401R

I have developed an application using the MSP432 Launch Pad.

I am transitioning to a production hardware design using the MSP432P401R ZXH (80-pin BGA).

BGA Part package markings:

MSP432

P401R

73A0T5W

G1

The application makes use of Timer 3A. The code running on the launch pad is able to set Timer 3A control and capture compare registers (i.e. reading back the register contents always yields the intended setting).

The SAME code running on the production hardware cannot set the necessary registers (i.e. reading back the register contents always yields 0x0000) and Timer 3A does not run.

(1) Is there an errata or other known problem with the above mentioned part/lot/mask revision?

(2) Since this is a BGA part, it is possible that one of the DVCC / AVCC / GND pins did not properly solder. I will note that all of the pcb vias have the correct voltage.

Is there a particular pin associated with power/gnd for Timer 3A? This might help us narrow are efforts to repair.

(3) Any other ideas/reasons why I would be unable to communicate with Timer 3A

(4) Are there any driver lib functions that may shed light on my problem?


MSP430F5234: How can I connect SDA and SCL to the BSL pins P1.1 and P1.2 if I want to use I2C BSL?

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Part Number:MSP430F5234

Hi,

I want to use I2C for BSL. How can I design the hardware and is there any example code for MSP430F5234 implementing I2C BSL? Thanks. 

Best regards,

Penny

MSP430FR5994: Enabling IPE using msp430-elf-gcc

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Part Number:MSP430FR5994

Hello,

I am using msp430-elf-gcc to create my project for MSP430FR5994. I want to use the IP Encapsulation feature present in my device. But all the documentation, such as SLAA685: MSP Code Protection Features and SLAU367O: device User's Guide, provide guidelines to setup IPE using CCS tools. I would like to do the same using msp430-elf-gcc. It is not sufficient to program the dedicated registers in my C code as IPE has to be setup/enabled at the time of boot process. Rather, it requires to be set in boot code (as described in section 9.6.1 of SLAU367)

I have the following questions on how to set up the following settings using msp430-elf-gcc.

1.In CCS, the linker command file(.cmd) contains a dedicated code section that defines the settings of Memory Protection Unit (MPU). How are the variables defined here mapped to the MPUIP registers on the device?

/****************************************************************************/
/* MPU/IPE SPECIFIC MEMORY SEGMENT DEFINITONS                               */
/****************************************************************************/

#ifdef _IPE_ENABLE
    #define IPE_MPUIPLOCK 0x0080
    #define IPE_MPUIPENA 0x0040
    #define IPE_MPUIPPUC 0x0020

    // Evaluate settings for the control setting of IP Encapsulation
    #if defined(_IPE_ASSERTPUC1)
        #if defined(_IPE_LOCK ) && (_IPE_ASSERTPUC1 == 0x08))
            fram_ipe_enable_value = (IPE_MPUIPENA | IPE_MPUIPPUC |IPE_MPUIPLOCK);
        #elif defined(_IPE_LOCK )
            fram_ipe_enable_value = (IPE_MPUIPENA | IPE_MPUIPLOCK);
        #elif (_IPE_ASSERTPUC1 == 0x08)
            fram_ipe_enable_value = (IPE_MPUIPENA | IPE_MPUIPPUC);
        #else
            fram_ipe_enable_value = (IPE_MPUIPENA);
        #endif
    #else
        #if defined(_IPE_LOCK )
            fram_ipe_enable_value = (IPE_MPUIPENA | IPE_MPUIPLOCK);
        #else
            fram_ipe_enable_value = (IPE_MPUIPENA);
        #endif
    #endif

    // Segment definitions
    #ifdef _IPE_MANUAL                  // For custom sizes selected in the GUI
        fram_ipe_border1 = (_IPE_SEGB1>>4);
        fram_ipe_border2 = (_IPE_SEGB2>>4);
    #else                           // Automated sizes generated by the Linker
        fram_ipe_border2 = fram_ipe_end >> 4;
        fram_ipe_border1 = fram_ipe_start >> 4;
    #endif

    fram_ipe_settings_struct_address = Ipe_settingsStruct >> 4;
    fram_ipe_checksum = ~((fram_ipe_enable_value & fram_ipe_border2 & fram_ipe_border1) | (fram_ipe_enable_value & ~fram_ipe_border2 & ~fram_ipe_border1) | (~fram_ipe_enable_value & fram_ipe_border2 & ~fram_ipe_border1) | (~fram_ipe_enable_value & ~fram_ipe_border2 & fram_ipe_border1));
#endif

#ifdef _MPU_ENABLE
    #define MPUPW (0xA500)    /* MPU Access Password */
    #define MPUENA (0x0001)   /* MPU Enable */
    #define MPULOCK (0x0002)  /* MPU Lock */
    #define MPUSEGIE (0x0010) /* MPU Enable NMI on Segment violation */

    __mpu_enable = 1;
    // Segment definitions
    #ifdef _MPU_MANUAL // For custom sizes selected in the GUI
        mpu_segment_border1 = _MPU_SEGB1 >> 4;
        mpu_segment_border2 = _MPU_SEGB2 >> 4;
        mpu_sam_value = (_MPU_SAM0 << 12) | (_MPU_SAM3 << 8) | (_MPU_SAM2 << 4) | _MPU_SAM1;
    #else // Automated sizes generated by Linker
        #ifdef _IPE_ENABLE //if IPE is used in project too
        //seg1 = any read + write persistent variables
        //seg2 = ipe = read + write + execute access
        //seg3 = code, read + execute only
               mpu_segment_border1 = fram_ipe_start >> 4;
               mpu_segment_border2 = fram_rx_start >> 4;
               mpu_sam_value = 0x1573; // Info R, Seg3 RX, Seg2 RWX, Seg1 RW
        #else
               mpu_segment_border1 = fram_rx_start >> 4;
               mpu_segment_border2 = fram_rx_start >> 4;
               mpu_sam_value = 0x1513; // Info R, Seg3 RX, Seg2 R, Seg1 RW
        #endif
    #endif
    #ifdef _MPU_LOCK
        #ifdef _MPU_ENABLE_NMI
            mpu_ctl0_value = MPUPW | MPUENA | MPULOCK | MPUSEGIE;
        #else
            mpu_ctl0_value = MPUPW | MPUENA | MPULOCK;
        #endif
    #else
        #ifdef _MPU_ENABLE_NMI
            mpu_ctl0_value = MPUPW | MPUENA | MPUSEGIE;
        #else
            mpu_ctl0_value = MPUPW | MPUENA;
        #endif
    #endif
#endif

2. Will IPE work from msp430-elf-gcc?

3. If yes to the previous question, the above code from linker command file defines the register control and protected memory segmentation of MPU segments. How can I set the same settings in the linker description file used in msp430-elf-gcc?

4. Will it suffice to make changes to linker description file to make IPE work? What else must be done to enable IPE from msp430-elf-gcc

Thank you,
Archanaa

MSP-EXP430F5529LP: I'm having trouble with the board not working on Windows 10 or Windows 7 computers.

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Part Number:MSP-EXP430F5529LP

I have two of these boards one fails on the BSL boot loader.

error - "failed to read data from RAM BSL.

Unsuccesful in starting the BSL restarting."

That's as far as it gets!

The second board is successful but fails to connect to the com port in the TDC1000_7200evm.

I have a third but I'm afraid to open the box!!!

I've read that this board has a high failure rate with working in Windows environments. Is there a fix yet? I really need to use this TDC7200 this next week in a demonstration?

MSP430FR5969: BSL scripter not working with lauchpad and MSP-FET

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Part Number:MSP430FR5969

Hi,

I am using MSP430FR5969 lauchpad + MSP430FR5969 launchPad + BSL scripter to verify the BSL function but I am facing some issues.

After I type in the command line the BSL-Scripter exited and I can not see any logs.  Here's my script I created based on your example. 

MODE FRxx UART COM49
RX_PASSWORD pass32_wrong.txt
DELAY 2000
RX_PASSWORD pass32_default.txt
RX_DATA_BLOCK msp430fr59xx_1.txt
SET_PC 0xF100

Hardware connection:

MSP-FET ->MSP430FR5969

Pin 2 -> VCC

Pin9 -> GND

Pin 8 -> TST(on J13)

Pin 11 -> RST(on J13)

Pin12 -> RXD(on J13)

Pin14 -> TXD(on J13)

I attached my code image as well. I am not quite sure how to determine the COM number and program counter. Thanks. 

(Please visit the site to view this file)

Best regards,

Penny

CCS/MSP432P401R: How to connect the analog input to MSP432P401R Launchpad in differential mode?

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Part Number:MSP432P401R

Tool/software: Code Composer Studio

Hi,

I am trying to use 14 bit ADC of MSP432P401R Launchpad in differential mode. Could you tell me the right way of connecting the analog input to the Launchpad? Right now, I am connecting the +ve terminal of the input to pin "P4.3" and the negative terminal of the input to "P4.2". Is this connection correct?

Mohammad Arifur Rahman

CCS/MSP430F5418A: Vacant Memory Interrupt occurs when executing instruction fetch from last 8 bytes of FLASH

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Part Number:MSP430F5418A

Tool/software: Code Composer Studio

Hi,

I've recently upgraded CCS from 7.X up to 8.1.0 and enabled the vacant memory access interrupt for the first time. After doing so I came accross very regular and strange SYSNMI_VECTOR interrupts every time a function executed that did an instruction fetch from address 0x25BFF.

On each compilation and attempt to debug the issue it kept moving as the function placed at the end location changed. Many red herring and dead end paths taken to come to this conclusion.

An exert from my .cmd file now reads;

MEMORY
{
    SFR                     : origin = 0x0000, length = 0x0010
    PERIPHERALS_8BIT        : origin = 0x0010, length = 0x00F0
    PERIPHERALS_16BIT       : origin = 0x0100, length = 0x0100

    BSL0                    : origin = 0x1000, length = 0x0200
    BSL1                    : origin = 0x1200, length = 0x0200
    BSL2                    : origin = 0x1400, length = 0x0200
    BSL3                    : origin = 0x1600, length = 0x01F0
    /* This will nuke the BSL entirely and NOT let it startup.
     * Upon next erasure cycle of the BSL3 area this will be set
     * to 0xFFFF which is an acceptable value. it must be 0xFFFF
     * or 0x0000. If this is NOT the case, then the device becomes
     * inoperable. And that would be bad :)
     *
     * Side note; this also ensures that the BSL is never accidentially
     * entered.
     */
    BSLZ                    : origin = 0x17F0, length = 0x0010, fill = 0x0000

    INFOD                   : origin = 0x1800, length = 0x0080
    INFOC                   : origin = 0x1880, length = 0x0080
    INFOB                   : origin = 0x1900, length = 0x0080
    INFOA                   : origin = 0x1980, length = 0x0080
	//RAMZ					: origin = 0x1C00, length = 0x0100, fill=0xA0A0
    RAM                     : origin = 0x1C00, length = 0x4000
    FLASH                   : origin = 0x5C00, length = 0xA380 , fill = 0x3FFF
    FLASH2                  : origin = 0x10000,length = 0x15B80, fill = 0x3FFF
    //Keep these bytes empty. Had VMAI errors raised in last section
    FLASH3                  : origin = 0x25B80,length = 0x80   , fill = 0x3FFF
    ....

SECTIONS
{
    .TI.noinit  : {} > RAM                  /* For #pragma noinit                */
    .bss        : {} > RAM                  /* Global & static vars              */
    .data       : {} > RAM                  /* Global & static vars              */
    .cio        : {} > RAM                  /* C I/O Buffer                      */
    .dbg        : {} > RAM
    .sysmem     : {} > RAM                  /* Dynamic memory allocation area    */
    /******************************** MEMORY HOLE ********************************/
    .stack      : {} > RAM (HIGH)           /* Software system stack             */

#ifndef __LARGE_CODE_MODEL__
    .text       : {} > FLASH                /* Code                              */
#else
    .text       : {} >> FLASH2 | FLASH      /* Code                              */
#endif
    .text:_isr  : {} > FLASH                /* ISR Code space                    */
    .cinit      : {} > FLASH                /* Initialization tables             */
#ifndef __LARGE_DATA_MODEL__
    .const      : {} > FLASH                /* Constant data                     */
#else
    .const      : {} >> FLASH | FLASH2      /* Constant data                     */
#endif

    .pinit      : {} > FLASH                /* C++ Constructor tables            */
    .binit      : {} > FLASH                /* Boot-time Initialization tables   */
    .init_array : {} > FLASH                /* C++ Constructor tables            */
    .mspabi.exidx : {} > FLASH              /* C++ Constructor tables            */
    .mspabi.extab : {} > FLASH              /* C++ Constructor tables            */
#ifdef __TI_COMPILER_VERSION__
  #if __TI_COMPILER_VERSION__ >= 15009000
    #ifndef __LARGE_CODE_MODEL__
    .TI.ramfunc : {} load=FLASH, run=RAM, table(BINIT)
    #else
    .TI.ramfunc : {} load=FLASH | FLASH2, run=RAM, table(BINIT)
    #endif
  #endif
#endif

    .bsl0.noinit      : {} > BSL0, type=NOLOAD
    .bsl1.noinit      : {} > BSL1, type=NOLOAD
    .bsl2.noinit      : {} > BSL2, type=NOLOAD
    .bsl3.noinit      : {} > BSL3, type=NOLOAD

    /* Nerf the BSLZ zone leaving the BSL disabled and JTAG access
     * enabled for development/release 
    */
    .bslz             : {} > BSLZ, fill=0x0000

    .infoA     : {} > INFOA              /* MSP430 INFO FLASH Memory segments */
    .infoB     : {} > INFOB
    .infoC     : {} > INFOC
    .infoD     : {} > INFOD

I'm filling all unused flash with 0x3FFF to ensure a proper code jump in case of onerous execution. The function that was being placed into the very last few bytes were

Proof _outc is at end of address range;

0x025BE2 _outc
0x025BE2 9D9D 0002 0004 2C07 4D2E 0ECF 531F
0x025BF0 4F8D 0000 4CCE 0000
0x025BF8 $C$L6
0x025BF8 539D 0004 4C4C 0110

Use linker directive;

MEMORY
{
...
FLASH3                  : origin = 0x25B80,length = 0x80   , fill = 0x3FFF
...
}
SECTIONS { ... .VMI.endFlash : { --library=rts430x_lc_sd_eabi.lib<snprintf.c.obj>(.text:_outc) } > FLASH3 (HIGH) ... }


Set breakpoint after program address 0x25BEE to be able to step through the code during run-time.

execute this code on startup;

/* Enable the FLASH and Memory access interrupts
 */
SFR_clearInterrupt(SFR_VACANT_MEMORY_ACCESS_INTERRUPT |
		SFR_FLASH_CONTROLLER_ACCESS_VIOLATION_INTERRUPT);
SFR_enableInterrupt(SFR_VACANT_MEMORY_ACCESS_INTERRUPT |
		SFR_FLASH_CONTROLLER_ACCESS_VIOLATION_INTERRUPT);


Pre & Post interrupt core registers


If I run the same hex file on a MSP430F5437A I do not get the same interrupt. I assume this is because the next flash address of 0x25C00 is valid and some kind of pre-fetch operation is occurring without checking for flash boundary limits.

If any instruction fetch operation occurs in the last 0x08 bytes of FLASH then a VMA Interrupt occurs. (I've tested 0x10 to 0x01 buffer zone from end of flash)

This will fail; Less than 8 bytes

//Keep these bytes empty. Had VMAI errors raised in last section
FLASH3 : origin = 0x25B00,length = 0xFA , fill = 0x3FFF
FLASH4 : origin = 0x25BFA,length = 0x06 , fill = 0x3FFF

This is OK; Equal or greater than 8 bytes

//Keep these bytes empty. Had VMAI errors raised in last section
FLASH3 : origin = 0x25B00,length = 0xF8 , fill = 0x3FFF
FLASH4 : origin = 0x25BF8,length = 0x08 , fill = 0x3FFF

(Please visit the site to view this file)

My working linker file for the MSP430F5418a project

This is my linker line for all my build options and inclusions.

"C:/ti/ccsv8/tools/compiler/ti-cgt-msp430_18.1.2.LTS/bin/cl430" -vmspx 
--data_model=small -O0 
--opt_for_speed=1 
--align_for_power 
--use_hw_mpy=F5 
--define=__MSP430F5418A__ 
--c99 
--float_operations_allowed=all 
--printf_support=full 
--gen_data_subsections=on 
--silicon_errata=CPU21 
--silicon_errata=CPU22 
--silicon_errata=CPU23 
--silicon_errata=CPU40 -z 
--heap_size=160 
--stack_size=2048 
--cinit_hold_wdt=on -i"C:/ti/ccsv8/ccs_base/msp430/include" 
-i"C:/ti/ccsv8/tools/compiler/ti-cgt-msp430_18.1.2.LTS/lib" 
-i"C:/ti/ccsv8/tools/compiler/ti-cgt-msp430_18.1.2.LTS/include" 
-i"C:/ti/ccsv8/ccs_base/msp430/lib/5xx_6xx_FRxx" 
-i"C:/ti/msp/MSP430Ware_3_80_04_05/iqmathlib/libraries/CCS/MPY32/5xx_6xx" 
--reread_libs 
--warn_sections 
--xml_link_info="MAT3_linkInfo.xml" 
--rom_model -o "MAT3.out" ## <obj list removed> ## "../lnk_msp430f5418a.cmd"  -llibc.a -llibmath.a -lIQmathLib.a -lIQmathLib_CCS_MPY32_5xx_6xx_CPUX_large_code_small_data.lib 




MSP430FR6989: About custom BSL

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Part Number:MSP430FR6989

Hello

I want to program FRAM custom BSL. However, I have never created a custom BSL.
Is there any reference application?
Or is there default BSL program software?

Regards.


RTOS/MSP430FR5994: MSP430fr5994 EUSCI_B3 SPI TI RTOS

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Part Number:MSP430FR5994

Tool/software: TI-RTOS

Hi All,

How to configure EUSCI B3 for spi in ti rtos. I am very difficult dma channel trigger and index from pdf file of data sheet. anyone knows how to configure it for spi in ti rtos? 

SPIEUSCIBDMA_Object spiEUSCIBDMAObjects[MSP_EXP430FR5994_SPICOUNT];
uint8_t spiEUSCIBDMAscratchBuf[MSP_EXP430FR5994_SPICOUNT];

const SPIEUSCIBDMA_HWAttrs spiEUSCIBDMAHWAttrs[MSP_EXP430FR5994_SPICOUNT] = {
{
.baseAddr = EUSCI_B3_BASE,
.clockSource = EUSCI_B_SPI_CLOCKSOURCE_SMCLK,
.bitOrder = EUSCI_B_SPI_MSB_FIRST,
.scratchBufPtr = &spiEUSCIBDMAscratchBuf[0],
.defaultTxBufValue = 0,

/* DMA */
.dmaBaseAddr = DMA_BASE,
/* Rx Channel */
.rxDMAChannelIndex = DMA_CHANNEL_5,
.rxDMASourceTrigger = DMA_TRIGGERSOURCE_18,//DMA_TRIGGERSOURCE_17
/* Tx Channel */
.txDMAChannelIndex = DMA_CHANNEL_4,
.txDMASourceTrigger = DMA_TRIGGERSOURCE_19 //DMA_TRIGGERSOURCE_16
}
};

const SPI_Config SPI_config[] = {
{
.fxnTablePtr = &SPIEUSCIBDMA_fxnTable,
.object = &spiEUSCIBDMAObjects[0],
.hwAttrs = &spiEUSCIBDMAHWAttrs[0]
},
{NULL, NULL, NULL},
};

/*
* ======== MSP_EXP430FR5994_initSPI ========
*/
void MSP_EXP430FR5994_initSPI(void)
{
/* EUSCIA3 */

/* SIMO/MOSI */
GPIO_setAsPeripheralModuleFunctionOutputPin(GPIO_PORT_P6, GPIO_PIN4, GPIO_PRIMARY_MODULE_FUNCTION);

/* SOMI/MISO */
GPIO_setAsPeripheralModuleFunctionInputPin(GPIO_PORT_P6, GPIO_PIN5, GPIO_PRIMARY_MODULE_FUNCTION);

/* CLK */
GPIO_setAsPeripheralModuleFunctionOutputPin(GPIO_PORT_P6, GPIO_PIN6, GPIO_PRIMARY_MODULE_FUNCTION);

SPI_init();
}

Best Regards

MSP430G2433: BSL warm start reacts differently than cold start

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Part Number:MSP430G2433

Hi,

Following the discussion https://e2e.ti.com/support/microcontrollers/msp430/f/166/t/704222 , I wanted to implement the BSL warm start to be able to update the msp firmware from our host controller without risking erasing the ADC calibration upon wrong password. 

When entering the BSL with the test/reset sequence (cold start), I can successfully do the whole flashing sequence.

But when entering the BSL with the warm start, the BSL replies to the Sync command with an ACK and then does not reply to any other command (I checked with a logic analyzer to be sure)

In both cases the whole communication process is exactly the same thing, the only difference being the warm VS cold start.

The command I use to enter the BSL warm start.

__disable_interrupt();

((void (*)(void))0x0C02)();

Do you have any idea what could be causing my issue? Or what I could check to understand the problem further?

MSP432E401Y: MSP432E LCD LIDD Controller- Hitachi HD44780 mode timing control question

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Part Number:MSP432E401Y

Hi,

I would like to know how to configure timing when LIDD working in Hitachi HD44780 mode.. Hitachi bus does not have WR nor RD pin.

In datasheet, LIDDCS0CFG/LIDDCS1CFG,  does write strobe/read strobe setting means E signal setting in Hitachi mode or something else? It is not so clear in datasheet description. Can you please help the answer?

    How can I choose to use 4bits or 8bits bus width? 

Regards

Andre

CCS/MSP430F5529: Can't exit LPM0 and/or ISR. CPU

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Part Number:MSP430F5529

Tool/software: Code Composer Studio

Hello,

I've been working through DriverLib examples and am trying to develop i2c driver to read/write to opt3001 ALS.  I'm relatively new to understanding interrupt & ISRs and believe I have some issue debugging my code in that at the end i2c_write, the device goes into LPM0+GIE, and the presumably through ISR, but I am unable to to step through OR exit the LPM & corresponding ISR.

Since I am new to interrupts, its distinctly possible that something is not correct with my ISR code, but since I can't step through it I am having a hard time pin pointing what is going wrong.  Line 113 is where I first run into the problem, but i expect that 155 will also have the same problem.

Anything look very wrong?

"MSP430: Can't Single Step Target Program: CPU is currently OFF and debugging capabilities will be limited."

/*
 * i2c_driver.c
 *
 *  Created on: July 16, 2014
 *      Author: a0272990
 *
 *  Copyright 2014 Texas Instruments Incorporated. All rights reserved.
 *
*/

//*****************************************************************************
// #includes
//*****************************************************************************
#include "driverlib.h"
#include "i2c_driver.h"
#include "QmathLib.h"
#include "IQmathLib.h"
#include "math.h"



//*****************************************************************************
// #defines
//*****************************************************************************

#define OPT3001_ADDRESS 0x44    //I2C address for OPT3001

#define CHECK_POLARITY 0x80     //Polarity flag (MSB of MSB)

//*****************************************************************************
// Global Variables
//*****************************************************************************

#define RXCOUNT 0x05
#define TXLENGTH 0x04

uint8_t i2c_transmitCounter = 0;    //Variable to store transmit status for I2C
uint8_t i2c_transmitData[40];        //
uint8_t *p_i2c_transmitData;        //Pointer to transmit data
uint8_t i2c_receivedCounter = 0;     //Variable to store receive status for I2C
uint8_t i2c_receivedBuffer[40];        //
uint8_t *p_i2c_receivedBuffer;        //Pointer to received data

//unsigned char receiveBuffer[10] = { 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01};
//unsigned char *receiveBufferPointer;
//unsigned char receiveCount = 0;

uint16_t    i2c_mode = 0;               //Variable to store i2c mode (tx or rx)
//*****************************************************************************
// I2C Library functions
//*****************************************************************************
void init_i2c(void)
{

    //Assign I2C pins to USCI_B1
    GPIO_setAsPeripheralModuleFunctionInputPin(GPIO_PORT_P4, GPIO_PIN1 + GPIO_PIN2);

       //Initialize Master
   USCI_B_I2C_initMasterParam param = {0};
   param.selectClockSource = USCI_B_I2C_CLOCKSOURCE_SMCLK;
   param.i2cClk = UCS_getSMCLK();
   param.dataRate = USCI_B_I2C_SET_DATA_RATE_100KBPS;
   USCI_B_I2C_initMaster(USCI_B1_BASE, &param);

   //Enable I2C Module to start operations
   USCI_B_I2C_enable(USCI_B1_BASE);

   //Enable master Receive interrupt
   USCI_B_I2C_enableInterrupt(USCI_B1_BASE, USCI_B_I2C_RECEIVE_INTERRUPT);

}

void i2c_write(uint8_t SLAVE_ADDRESS)
{


    //Initialize Master
    USCI_B_I2C_initMasterParam param = {0};
    param.selectClockSource = USCI_B_I2C_CLOCKSOURCE_SMCLK;
    param.i2cClk = UCS_getSMCLK();
    param.dataRate = USCI_B_I2C_SET_DATA_RATE_400KBPS;
    USCI_B_I2C_initMaster(USCI_B1_BASE, &param);

    //Specify slave address
    USCI_B_I2C_setSlaveAddress(USCI_B1_BASE, SLAVE_ADDRESS
        );

    //Set Transmit mode
    USCI_B_I2C_setMode(USCI_B1_BASE,
        USCI_B_I2C_TRANSMIT_MODE
        );

    //Enable I2C Module to start operations
    USCI_B_I2C_enable(USCI_B1_BASE);


    while (1)
    {
        //Enable transmit Interrupt
        USCI_B_I2C_clearInterrupt(USCI_B1_BASE,  USCI_B_I2C_TRANSMIT_INTERRUPT);
        USCI_B_I2C_enableInterrupt(USCI_B1_BASE, USCI_B_I2C_TRANSMIT_INTERRUPT );

        //Delay between each transaction
        __delay_cycles(50);  //Replace with timer ISR?

        //Load TX byte counter
        i2c_transmitCounter = 1;

        //Initiate start and send first character
        USCI_B_I2C_masterSendMultiByteStart(USCI_B1_BASE, i2c_transmitData[0] );

        //Enter LPM0 with interrupts enabled
        __bis_SR_register(LPM0_bits + GIE);
        __no_operation();

        //Delay until transmission completes
        while (USCI_B_I2C_isBusBusy(USCI_B1_BASE)) ;
    }
}

void i2c_read_byte(uint8_t SLAVE_ADDRESS, uint8_t BYTE_COUNT)
{

      //Initialize Master
      USCI_B_I2C_initMasterParam param = {0};
      param.selectClockSource = USCI_B_I2C_CLOCKSOURCE_SMCLK;
      param.i2cClk = UCS_getSMCLK();
      param.dataRate = USCI_B_I2C_SET_DATA_RATE_100KBPS;
      USCI_B_I2C_initMaster(USCI_B1_BASE, &param);

      //Specify slave address
      USCI_B_I2C_setSlaveAddress(USCI_B1_BASE, SLAVE_ADDRESS);

      //Set receive mode
      USCI_B_I2C_setMode(USCI_B1_BASE, USCI_B_I2C_RECEIVE_MODE);

      //Enable I2C Module to start operations
      USCI_B_I2C_enable(USCI_B1_BASE);

      //Enable master Receive interrupt
      USCI_B_I2C_enableInterrupt(USCI_B1_BASE, USCI_B_I2C_RECEIVE_INTERRUPT);

      //wait for bus to be free
      while (USCI_B_I2C_isBusBusy(USCI_B1_BASE )) ;

      while (1)
      {
          p_i2c_receivedBuffer = (unsigned char *)i2c_receivedBuffer;
          i2c_receivedCounter = sizeof i2c_receivedBuffer;

          //Initialize multi reception
          USCI_B_I2C_masterReceiveMultiByteStart(USCI_B1_BASE);

          //Enter low power mode 0 with interrupts enabled.
          __bis_SR_register(LPM0_bits + GIE);
          __no_operation();
      }
}


void OPT3001_init(void)
{

    uint8_t OPT3001_Config_SW_reset[3] =
    {
        0x01,   //CDC Config register address
        0xC2,   //MSB of configuration (sets 100ms conversion time, single shot mode)
        0x10    //LSB of configuration
    };

    p_i2c_transmitData = (uint8_t *)OPT3001_Config_SW_reset;    //Transmit array start address
    i2c_transmitCounter = sizeof OPT3001_Config_SW_reset;       //Load transmit byte counter
    i2c_write(OPT3001_ADDRESS);
    __delay_cycles(DELAY_10_MS);
}

int32_t OPT3001_singleRead(void)
{

    //uint8_t CDC_Config[2] = {0};    //Test variable
    uint8_t Lux_Meas1_MSB[2] = {0x00,0x00}; //MSBs of capacitance MEAS1
    //uint32_t luxVal=0;

    int32_t Lux_MEAS1 = 0;  //24-bit Lux value from MEAS1 (32bit variable)

    uint8_t OPT3001_initMEAS1[3] =
    {
        0x01,   //OPT Config register address
        0xC2,   //MSB of configuration (sets 100ms conversion time, single shot mode)
        0x10    //LSB of configuration
    };

    const uint8_t OPT3001_ResultAddr[1] = {0x00};   //Lux_MEAS1_MSB register address

    p_i2c_transmitData = (uint8_t *)OPT3001_initMEAS1;      //Transmit array start address
    i2c_transmitCounter = sizeof OPT3001_initMEAS1;         //Load transmit byte counter
    i2c_write(OPT3001_ADDRESS);

    __delay_cycles(DELAY_10_MS);

    p_i2c_transmitData = (uint8_t *)OPT3001_ResultAddr; //Transmit array start address
    i2c_transmitCounter = sizeof OPT3001_ResultAddr;        //Load transmit byte counter
    i2c_write(OPT3001_ADDRESS);

    p_i2c_receivedBuffer = (uint8_t *)Lux_Meas1_MSB;          //Receive array start address
    i2c_read_byte(OPT3001_ADDRESS, sizeof Lux_Meas1_MSB);   //Read two bytes of lux data form result register

    Lux_MEAS1 =  0x0FFF & (uint16_t)Lux_Meas1_MSB[0] << 8 | (uint16_t)Lux_Meas1_MSB[1];
    int8_t exp = Lux_Meas1_MSB[0]>> 4;  //exponent is top four bits
    Lux_MEAS1 = 0.01 * pow(2,exp) * Lux_MEAS1;
    return Lux_MEAS1;
}
//******************************************************************************
//
//This is the USCI_B1 interrupt vector service routine.
//
//******************************************************************************
#if defined(__TI_COMPILER_VERSION__) || defined(__IAR_SYSTEMS_ICC__)
#pragma vector=USCI_B1_VECTOR
__interrupt
#elif defined(__GNUC__)
__attribute__((interrupt(USCI_B1_VECTOR)))
#endif
void USCI_B1_ISR (void)
{
    switch (__even_in_range(UCB1IV,12)){
        case USCI_I2C_UCTXIFG:
        {
            //Check TX byte counter
            if (i2c_transmitCounter < sizeof i2c_transmitData)
            {
                //Initiate send of character from Master to Slave
                USCI_B_I2C_masterSendMultiByteNext(USCI_B1_BASE,
                    i2c_transmitData[i2c_transmitCounter]
                    );

                //Increment TX byte counter
                i2c_transmitCounter++;
            }
            else
            {
                //Initiate stop only
                USCI_B_I2C_masterSendMultiByteStop(USCI_B1_BASE);

                //Clear master interrupt status
                USCI_B_I2C_clearInterrupt(USCI_B1_BASE,
                    USCI_B_I2C_TRANSMIT_INTERRUPT);

                //Exit LPM0 on interrupt return
                __bic_SR_register_on_exit(LPM0_bits);
            }
            break;
        }

        case USCI_I2C_UCRXIFG:
        {
            //Decrement RX byte counter
            i2c_receivedCounter--;

            if (i2c_receivedCounter)
            {
                if (i2c_receivedCounter == 1)
                {
                    //Initiate end of reception -> Receive byte with NAK
                    *p_i2c_receivedBuffer++ =
                        USCI_B_I2C_masterReceiveMultiByteFinish(
                                USCI_B1_BASE
                            );
                }
                else
                {
                    //Keep receiving one byte at a time
                    *p_i2c_receivedBuffer++ = USCI_B_I2C_masterReceiveMultiByteNext(
                            USCI_B1_BASE
                        );
                }
            }
            else
            {
                //Receive last byte
                *p_i2c_receivedBuffer = USCI_B_I2C_masterReceiveMultiByteNext(
                        USCI_B1_BASE
                    );
                __bic_SR_register_on_exit(LPM0_bits);
            }

            break;
        }
    }
}


MSP430FR5969-SP: TID-SEE and reliability (environmental test)

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Part Number:MSP430FR5969-SP

Hi,

Is it possible to get SEL (Single Event Latch-up) data for MSP430F5969-SP?

In January 2018, (on the forum) you said you will produce a report on SEU (Single Event Upset) in the future. Do you have a date. Same question about the SET.

Concerning the TID (Total Ionizing Dose) results for MSP430F5969-SP, I'm surprised that the dose rate was an high rate for a biCMOS. You know that the behavior of a biCMOS die depends on the dose rate, why do you use an hight dose rate for biCMOS die?

As there is nothing written in the datasheet, would you mind to share the screening flow/testing and qualification groups performed on this component?

Thanks and best regards,

Jacky

that the  e do not test our EP devices for radiation effects. Only our devices targeted for the space market.
All available TI radiation data is available here: www.ti.com/.../space.html
We have just released the MSP430FR5969-SP.
Single Event Latchup (SEL) Immune to 72 MeV.cm2/mg at 125°C.
Radiation Lot Acceptance Tested to 50 krad


Any other EMC test data available?

Thanks and Regards,

Ankit

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