Part Number:MSP432P401R
Hello, I'm new to programming the MSP432 and I have problems with my code. What I want to achieve is getting audio from my microphone electret (Adafruit MAX9814), sample the signal at 44.1 kHz (the signal would be converted from analog coming from the microphone to digital), convert that digital signal back to analog and output it to a speaker so I can listen to the sound. I'm not hearing anything but static so far. Can I get guidance? I'll leave my code below.
#include "msp.h"
#include <stdint.h>
void main(void)
{
WDT_A->CTL = WDT_A_CTL_PW | WDT_A_CTL_HOLD; // stop watchdog timer
//GPIO Setup
P4->DIR &= ~(BIT7);// Analog input channel A6
P4->SEL0 |= BIT7; // Enable A/D channel A6
P4->SEL1 |= BIT7; // P4.7 - analog input
P5->DIR |= BIT4; // Output to speaker
P5->SEL0 |= BIT4;
//while(PCM->CTL1 & PCM_CTL1_PMR_BUSY);
//PCM->CTL0 = PCM_CTL0_KEY_VAL | PCM_CTL0_AMR__AM_LDO_VCORE1;
//while(PCM->CTL1 & PCM_CTL1_PMR_BUSY);
//Set clock to 24 MHz using DCO
CS->KEY = CS_KEY_VAL; //Unlock CS registers
CS->CTL0 = CS_CTL0_DCOEN | CS_CTL0_DCORSEL_4; //Choose 24 MHz clock speed
CS->CTL1 = CS_CTL1_SELS_3 | CS_CTL1_SELM_3 ; //Use DCOCLK as source for MCLK, SMCLK + HSMCLK
CS->KEY = 0; //Re-lock CS registers
// ADC14 Setup
ADC14->CTL0 &= ~ADC14_CTL0_ENC; // Reset ENC bit for configuration
ADC14->CTL0 = ADC14_CTL0_PDIV_1 | // Pre-divide clock by 4
ADC14_CTL0_SHS_1 | // Timer A0 trigger
ADC14_CTL0_SHP | // Pulse mode
ADC14_CTL0_DIV_5 | // divide clock by 6
ADC14_CTL0_SSEL_3 | // ADC clock source is MCLK
ADC14_CTL0_CONSEQ_2 | // Repeat-single channel
ADC14_CTL0_SHT0_2 | // Sampling length of 16 ADC clock cycles
ADC14_CTL0_ON; // ADC module on
ADC14->CTL1 = ADC14_CTL1_RES_3; // 14-bit resolution
ADC14->MCTL[0] = ADC14_MCTLN_INCH_6; // ref+ = AVcc, channel = A1
// Timer_A0 Setup
TIMER_A0->CCTL[0] = TIMER_A_CCTLN_CCIE; //Enable CC interrupt
TIMER_A0->CTL = TIMER_A_CTL_TASSEL_2 | // SMCLK as source for timer
TIMER_A_CTL_ID_1 | // Divide clock by 2 -> 48 MHz / 2 = 24 MHz
TIMER_A_CTL_MC_1 | // Up mode
TIMER_A_CTL_CLR | // Clear timer count
TIMER_A_CTL_IE; // Enable overflow interrupt
TIMER_A0->CCR[0] = 544; // 24 MHz / 44.1 kHz = 544
// T = (TAxCCR0+1) / f_clk = (544+1) / 24 MHz = 2.27x10^(-5)
TIMER_A0->CCTL[1] = TIMER_A_CCTLN_OUTMOD_7; // Set/Reset for trigger halfway through the cycle
// Enable global interrupt
__enable_irq();
NVIC->ISER[0] = 1 << ((ADC14_IRQn) & 31); // Enable ADC interrupt in NVIC module
// Wake up on exit from ISR
SCB->SCR &= ~SCB_SCR_SLEEPONEXIT_Msk;
// Ensures SLEEPONEXIT takes effect immediately
__DSB();
while(1)
{
ADC14->CTL0 |= ADC14_CTL0_ENC | ADC14_CTL0_SC; // Start conversion-software trigger
__sleep();
__no_operation(); // For debugger
}
}
void ADC14_IRQHandler(void)
{
while((ADC14->IFGR0 & ADC14_IFGR0_IFG6) == 0); // waiting for conversion to be done
//audio = ADC14->MEM[0]; // Conversion stored in audio variable.
P5->DIR ^= BIT4;
}
//void TA0_A0_IRQHandler(void)
//{
// TIMER_A0->CCTL[0] &= ~TIMER_A_CCTLN_CCIFG;
//}
