Quantcast
Channel: MSP low-power microcontroller forum - Recent Threads
Viewing all 22218 articles
Browse latest View live
↧

MSP430FR5994: Main Memory Bootloader Crashing

September 3, 2019, 9:52 am
$
0
0

Part Number: MSP430FR5994

                                Crashing Boot Loader

Dear Sirs:

     I’m writing a bootloader for the msp430fr5994.  It has the following memory:

 boot program from 0x5000 to 0x5fff

run program from 0x10000 to 0x1ffff

arrays from 0x4000

variables at around 0x2,000

And of course vectors at around 0xffff

 

  The new program downloaded by the bootloader is an SREC hex file generated by the compiler.

It contains data starting at 0x4000 (because there is an array there) , the bootloader itself at 0x5000 and the new program at 0x10000.

   The bootloader acts as a sort of executive that is called at startup time by the main memory.

It returns by user command and returns by doing a BOR restart.  A variable in upper memory signals to the main program that it has been called.

    What is different about this arraignment is that the bootloader is a module in the main code that is called during startup.  However it is prevented from being  downloaded by the bootloader but is put into memory by the TI debugger when it puts the rest of the program into memory first time.  Subsequent program updates in the field are supposed to be done using the bootloader.

   When the new program is downloaded it is stored from 0x24000 to 0x3ffff.  Then if its checksum

Is ok it is programmed into run memory (at 0x4000 and 0xffff and  0x10000) by the bootloader.

 

Failure mode:

     Everything works ok if the bootloader downloads the hex file for the program it resides in but if a different revision is downloaded the bootloader crashes when it is attempted to program the downloaded program into run memory.  Then the bootloader crashes and ceases to operate correctly.  It is almost as though the prog write triggers a stray interrupt.

     Anyone have suggestions?

Thanks,

John

 

    

 

↧
Search

MSP430I2041: Issue : RST pull-up/cap for normal operation -vs- RST pull-up/cap for FET emulation.

September 3, 2019, 10:53 am
$
0
0

Part Number: MSP430I2041

Support,

We have a critical issue that is preventing us from moving to volume production!   We are using MSP430i2041 in an Energy Metering Product and seeing intermittent issues where the MSP is reporting Zero Current or Zero Energy with a load connected.  Another issue, we see correct Voltage and Current based on the load but Energy never increases.  In both these cases an MSP reset solves the issue.  We suspect the device is getting reset due to a glitch.  Although this doesn't explain the situation above, we would expect all readings should go to ZERO

Maybe a related issue, we are unable to program via FET using either 10nF or 2.2nF cap on the RSTn line per the data sheet.  We have to remove the cap altogether, which definitely makes RSTn susceptible to glitches.  Although, we no CAP, and scoping Vcc and RSTn signals, we can inject a high frequency glitch in the order of 'ns' and the system does not reset.  This would simulate different loads on the main line. 

We thought the HOST MCU was interfering since it controls the RSTn signal during normal use, but at power up, the signal from the HOST is set to High-Z.

We need to know what CAP to use on the RSTn line to accommodate 

1. Production line programming with FET - while HOST MCU pin is in High-Z

2. sufficient filtering for normal operation

We are using the FET with Elprotronic tool.  There is no option to slow down the JTAG clock.  Can you suggest another programming tool that would allow us to slow down the SBW clock?

Regards,

↧
↧

MSP430I2041: IAR generated .txt file to use with UNIFLASH tool; Does it inherit JTAG speed under IAR FET settings

September 3, 2019, 1:01 pm
$
0
0

Part Number: MSP430I2041

Support,

Does IAR workbench .txt output file have JTAG speed encoded into it?

Project Options : Options --> Debugger --> FET Debugger --> JTAG speed is there but it looks like it is after the linker stage.

Regards,

Marc

↧

MSP430F5342: What is the transfer function for the ADC12 integrated temperature sensor?

September 3, 2019, 1:09 pm
$
0
0

Part Number: MSP430F5342

Hi MSP430 Team,

I am posting this question on behalf of my customer.

What I am looking for is the transfer equation for the ADC12 integrated temperature sensor. When looking at the manual there is a transfer function listed for the ADC10 under section 27.2.9 but there is no transfer function listed under section 28.2.8. So I am looking for that transfer function.

 Thank you!
Lauren

↧

MSP432P401M: Firmware upload by USART

September 3, 2019, 1:32 pm
$
0
0

Part Number: MSP432P401M

is avialable a software for upload firmware by USART (P1.2 and P1.3 pin) ?
I have maked the output in TI Format *.TXT, and invoke :

MAP_Interrupt_disableMaster();

BSL_INVOKE(BSL_UART_INTERFACE);

but do not found in web TI.com any free software for upload the firmware by USART

↧
↧

MSP430FR2433: DCO = 4.9152MHz is unstable after reset in cold environments.

September 3, 2019, 3:33 pm
$
0
0

Part Number: MSP430FR2433

Hi community member,

My customer was further verification.
As a result, the same problem occurred in LaunchPad (MSP-EXP430FR2433).

If reset in a low temperature environment (About -35C),
DCO will not oscillate 4.9152MHz even with LaunchPad.
In this case, DCORSEL is 010b.

I would like to know your views on this issue.
Please reply as soon as possible.


Best regards.
Cruijff

↧

MSP-GANG: cannnot write multiple units at the same time

September 3, 2019, 5:23 pm
$
0
0

Part Number: MSP-GANG

We use TI's MSP-GANG-PROGRAMER.

Now there is a problem. I'd like to ask you for a solution.

Target is FR69721 powered by external 2.4V.

This is the schematic drawing for the connection on our board

One device will succeed, but multiple devices will all fail

Please advise.

↧

MSP430FR2311: msp430-gcc elf file format details?

September 3, 2019, 7:41 pm
$
0
0

Part Number: MSP430FR2311

I'm looking for details on the msp430 .elf file format. I looked through the msp430 gcc manual and didn't see any mention of it. Does anyone know where I can find these details? I have to write a script to parse the elf for packing into another mcu's firmware.

↧
Search

MSP430FR5969-SP: eval boards

September 3, 2019, 8:04 pm
$
0
0

Part Number: MSP430FR5969-SP

Team, 

A few common questions Id like to have forum answers to:

  1. We are interested in testing with the launchpad MSP (http://www.ti.com/tool/MSP-EXP430FR5969). If we write code to program this MSP, will the code translate directly to the MSP430-FR5969-SP part (more specifically, M4FR5969SRGZT-MLS) and perform as seen on the launchpad?
  2. Does the MSP430 have an internal temperature sensor? It appears so from the datasheet, but we would like a confirmation since the temperature sensor was not listed as a feature for the MSP430-FR5969-SP.
  3. What are the main differences in testing with the launchpad MSP and the target development board? http://www.ti.com/tool/MSP-TS430RGZ48C
  1. Would programming for the target development board translate directly to the programming for the MSP430 and perform as expected?
  2. Would one eval board yield more insight in debugging or more closely model the actual MSP430? We would appreciate your recommendation.
  • We are designing a schematic of our system layout with MSP430. We found some sample schematics on the launchpad board datasheet, but are there any available layouts for the target development board that we could use for guidance?

↧
↧

MSP430FR6877: Disable SVS

September 3, 2019, 10:03 pm
$
0
0

Part Number: MSP430FR6877

Hello experts,

My customer has question for MSP430FR6877.

During noise test, MAP430FR6877's CPU reset function is on.

To prevent this, my customer wants to know the register which disable SVS at active mode.

Could you share the way how to disable SVS?

Thanks and best regards,

Ryo Akashi

↧

MSP430FR6043: real FFT/iFFT calculation using LEA

September 3, 2019, 11:54 pm
$
0
0

Part Number: MSP430FR6043

Hello, 

We are evaluating real FFT/iFFT with MSP430FR6043, and found an issue as below:

  • Convert time domain signal A to frequency domain signal B using msp_fft_fixed_q15().
  • Convert frequency domain signal B back to domain signal C using msp_ifft_fixed_q15().
  • It’s found that A is totally different from C, and it is not caused by precision lost.

Can you help to look into this?

Thanks for your help.

Chaofan

↧

MSP430FR5994: MSP low-power microcontroller forum

September 4, 2019, 12:00 am
$
0
0

Part Number: MSP430FR5994

Hello, 

We are evaluating real FFT/iFFT with MSP430FR6043, and found an issue as below:

  • Convert time domain signal A to frequency domain signal B using msp_fft_fixed_q15().
  • Convert frequency domain signal B back to domain signal C using msp_ifft_fixed_q15().
  • It’s found that A is totally different from C, and it is not caused by precision lost.

Can you help to look into this?

Thanks for your help.

Chaofan

↧

MSP430FR2433: MSP430FR2433 EVM Kit

September 4, 2019, 12:09 am
$
0
0

Part Number: MSP430FR2433

My customer has tested the MSP430FR2433 EVM kit alone and it is working fine. Now they are trying to validate the MSP430FR2433 I2C BSL mode with our gateway board and they have some queries on this point.

The EVM kit working IO voltage is 3.3V and the customer's  gateway board working IO voltage is 1.8V. So they want to make changes on the EVM kit to make it work with 1.8V, so that they can directly wire up the EVM kit with their gateway board to validate the I2C BSL mode.

 

Could you please tell me that Is it possible to make the EVM kit to work with 1.8V?

If so, please suggest the changes to be made on the EVM kit to make it work with 1.8V ASAP.

↧
↧

A issue on Slau320——《MSP430™ Programming Via the JTAG Interface User's Guide》

September 4, 2019, 12:34 am
$
0
0

Hi everyone，

I have some issues on understanding the following function

TCLKstrobes(uint16_t strobeAmount)

and turn to your help.

1) Programing Flash need a CLK between 257KHz and 476KHz accoring to the F4xx user guider. So
TCLKstrobes(uint16_t strobeAmount) is generate this CLK , Am I right?

2)
ClrTCLK();
IR_Shift(IR_ADDR_16BIT);
DR_Shift16(0x012A); // FCTL2 address
IR_Shift(IR_DATA_TO_ADDR);
DR_Shift16(0xA540); // MCLK is source, DIV=1
SetTCLK();

This part code write 0xA540 to FCTL2, that means Flash controller CLK source from MCLK /2.

In my understanding , In JTAG mode, TCLK act as a MCLK of the core.

Here comes the question:

TCLKstrobes should generate a CLK of (257KHz~476KHz) or double the Frequency(514KHz~952KHz)?

B.R

Seafesse

void EraseFLASH(word EraseMode, word EraseAddr)
{
    word StrobeAmount = 4820;       // default for Segment Erase
    word i, loopcount = 1;          // erase cycle repeating for Mass Erase
    word FCTL3_val = SegmentInfoAKey;   // SegmentInfoAKey holds Lock-Key for Info
                                        // Seg. A     


    if ((EraseMode == ERASE_MASS) || (EraseMode == ERASE_MAIN))
    {
        if(DeviceHas_FastFlash())
        {
            StrobeAmount = 10600;        // Larger Flash memories require
        }
        else
        {
            StrobeAmount = 5300;        // Larger Flash memories require
            loopcount = 19;             // additional cycles for erase.
        }
    }
    HaltCPU();

    for (i = loopcount; i > 0; i--)
    {
        ClrTCLK();
        IR_Shift(IR_CNTRL_SIG_16BIT);
        DR_Shift16(0x2408);         // set RW to write
        IR_Shift(IR_ADDR_16BIT);
        DR_Shift16(0x0128);         // FCTL1 address
        IR_Shift(IR_DATA_TO_ADDR);
        DR_Shift16(EraseMode);      // Enable erase mode
        SetTCLK();

        ClrTCLK();
        IR_Shift(IR_ADDR_16BIT);
        DR_Shift16(0x012A);         // FCTL2 address
        IR_Shift(IR_DATA_TO_ADDR);
        DR_Shift16(0xA540);         // MCLK is source, DIV=1
        SetTCLK();

        ClrTCLK();
        IR_Shift(IR_ADDR_16BIT);
        DR_Shift16(0x012C);         // FCTL3 address
        IR_Shift(IR_DATA_TO_ADDR);
        DR_Shift16(FCTL3_val);      // Clear FCTL3; F2xxx: Unlock Info-Seg. A by toggling LOCKA-Bit if required,
        SetTCLK();

        ClrTCLK();
        IR_Shift(IR_ADDR_16BIT);
        DR_Shift16(EraseAddr);      // Set erase address
        IR_Shift(IR_DATA_TO_ADDR);
        DR_Shift16(0x55AA);         // Dummy write to start erase
        SetTCLK();

        ClrTCLK();
        IR_Shift(IR_CNTRL_SIG_16BIT);
        DR_Shift16(0x2409);         // Set RW to read


        TCLKstrobes(StrobeAmount);  // Provide TCLKs


        IR_Shift(IR_CNTRL_SIG_16BIT);
        DR_Shift16(0x2408);         // Set RW to write
        IR_Shift(IR_ADDR_16BIT);
        DR_Shift16(0x0128);         // FCTL1 address
        IR_Shift(IR_DATA_TO_ADDR);
        DR_Shift16(0xA500);         // Disable erase
        SetTCLK();
    }
    // set LOCK-Bits again
    ClrTCLK();
    IR_Shift(IR_ADDR_16BIT);
    DR_Shift16(0x012C);         // FCTL3 address
    IR_Shift(IR_DATA_TO_ADDR);
    DR_Shift16(FCTL3_val);      // Lock Inf-Seg. A by toggling LOCKA (F2xxx) and set LOCK again
    SetTCLK();

    ReleaseCPU();    
}

↧

CCS/MSP430FR6972: msp430fr6972

September 4, 2019, 12:44 am
$
0
0

Part Number: MSP430FR6972

Tool/software: Code Composer Studio

Hello, 

I am using MSP430FR6972.

I want to make automatic baud rate detection program.

But I am not understanding as,

how to make the program?

Can you help me to make the program.

I was going through the data sheet,

but was unable to understand.

So please help me.

If any reference/code.

Please help.

I am waiting for your reply,

please do reply.

regards,

Srijit.

↧
Search

MSP430FR5949: MSP430FR5949

September 4, 2019, 1:45 am
$
0
0

Part Number: MSP430FR5949

It is working perfectly but i have some doubt in this SYSRSTIV comes 0x0016 when we come of the ieration but after if condition SYSTSTIV comes like 0x000 why? can you please explain 

#include <msp430.h>

int main(void) {
// WDTCTL = WDTPW | WDTHOLD; // Stop watchdog timer

if (SYSRSTIV ==SYSRSTIV_WDTTO) {

switch(SYSRSTIV_WDTTO){
case SYSRSTIV_NONE: /* No Interrupt pending */
_no_operation();
break;
case SYSRSTIV_BOR : /* SYSRSTIV : BOR */
_no_operation();
break;
case SYSRSTIV_RSTNMI: /* SYSRSTIV : RST/NMI */
_no_operation();
break;
case SYSRSTIV_DOBOR: /* SYSRSTIV : Do BOR */
_no_operation();
break;
case SYSRSTIV_LPM5WU: /* SYSRSTIV : Port LPM5 Wake Up */
_no_operation();
break;
case SYSRSTIV_SECYV : /* SYSRSTIV : Security violation */
_no_operation();
break;
case SYSRSTIV_RES0C: /* SYSRSTIV : Reserved */
_no_operation();
break;
case SYSRSTIV_SVSHIFG: /* SYSRSTIV : SVSHIFG */
_no_operation();

break;
case SYSRSTIV_RES10: /* SYSRSTIV : Reserved */
_no_operation();
break;
case SYSRSTIV_RES12: /* SYSRSTIV : Reserved */
_no_operation();
break;
case SYSRSTIV_DOPOR: /* SYSRSTIV : Do POR */
_no_operation();
break;
case SYSRSTIV_WDTTO: /* SYSRSTIV : WDT Time out */
_no_operation();
break;
case SYSRSTIV_WDTKEY: /* SYSRSTIV : WDTKEY violation */
_no_operation();
break;
case SYSRSTIV_FRCTLPW: /* SYSRSTIV : FRAM Key violation */
_no_operation();
break;
case SYSRSTIV_UBDIFG: /* SYSRSTIV : FRAM Uncorrectable bit Error */
_no_operation();
break;
case SYSRSTIV_PERF: /* SYSRSTIV : peripheral/config area fetch */
_no_operation();
break;
case SYSRSTIV_PMMPW: /* SYSRSTIV : PMM Password violation */
_no_operation();
break;
case SYSRSTIV_MPUPW: /* SYSRSTIV : MPU Password violation */
_no_operation();
break;
case SYSRSTIV_CSPW: /* SYSRSTIV : CS Password violation */
_no_operation();
break;
case SYSRSTIV_MPUSEGPIFG: /* SYSRSTIV : MPUSEGPIFG violation */
_no_operation();
break;
case SYSRSTIV_MPUSEGIIFG: /* SYSRSTIV : MPUSEGIIFG violation */
_no_operation();
break;
case SYSRSTIV_MPUSEG1IFG: /* SYSRSTIV : MPUSEG1IFG violation */
_no_operation();
break;
case SYSRSTIV_MPUSEG2IFG: /* SYSRSTIV : MPUSEG2IFG violation */
_no_operation();
break;
case SYSRSTIV_MPUSEG3IFG: /* SYSRSTIV : MPUSEG3IFG violation */
_no_operation();
break;
case SYSRSTIV_ACCTEIFG: /* SYSRSTIV : ACCTEIFG access time error */
_no_operation();
break;
default:

break;
}
}
while(1);
}

↧

MSP430FR6043: GUI UPS/DNS Gap timing

September 4, 2019, 6:18 am
$
0
0

Part Number: MSP430FR6043

Hello,
I had a look on to the "UPS and DNS Gap" and "UPS0 to UPS1 Gap" timings with a scope. The timing are a higher than configured with the GUI.
I set the UPS/DNS gap to 8000us but measure 9.7ms. The UPS0/UPS1 gap is set to 150ms but measured 187ms.

GUI version: 02_20_00_19
SW version: 02_20_00_12

Regards, Holger

↧
↧

MSP430F5435A: Segment B corruption

September 4, 2019, 7:23 am
$
0
0

Part Number: MSP430F5435A

Hello,

I have Segment B corruption on around 50 Msp430F5435A (rev F and rev H). All the segments B are written with 0xFF. For these msp I have several SVSH and SVSL resets type. Do you know which could cause this corruption. The msp are powered by a battery.

It's critical because I store a CRC in this flash area.

Thank you for your help.

↧

MSP430FR2311: BSL CRC implementation?

September 4, 2019, 7:46 am
$
0
0

Part Number: MSP430FR2311

Hi,

I have a function in my application code which calculates the hash of the entire FRAM region of my chip. It is implemented in the code attached. If I were to have the same arguments to the BSL (namely, the start address being 0xf100 and the length being 1920 16bit words), is this an equivalent operation to what I have below?

Also what is the 16 bit polynominal used? I'm using 0x1021 for CRC16 CCITT, but I don't seem to get the same result. 

// Address of the first and last word
#define FIRMWARE_START_ADDRESS  FRAM_START
#define FIRMWARE_FRAM_SIZE      1920
static void CrcFirmware(void)
{
  uint16_t i;
  uint16_t* flash_ptr = (uint16_t*)FIRMWARE_START_ADDRESS;
  
  // Write the first word in to initalize crc hardware
  CRCINIRES = flash_ptr[0];
  
  for (i = 1; i < FIRMWARE_FRAM_SIZE; i++)
  {
    CRCDI = flash_ptr[i];
  }
  
  // Save the result
  firmware_crc = CRCINIRES;
}

↧

CCS/MSP432P401R: How to configure the DMA for ADC_14 to transfer 8192 samples to the buffer at a time?

September 4, 2019, 8:22 am
$
0
0

Part Number: MSP432P401R

Tool/software: Code Composer Studio

Hi,

I am using "boostxl_edumkii_microphonefft_msp432p401r_MSP_EXP432P401R_nortos_ccs" example project to do FFT where the sampling frequency is 8192 Hz and those 8192 samples need to be transferred to the buffer before doing the FFT. But the DMA can transfer maximum 1024 samples from the memory to the buffer. 

Is there any way to transfer the 8192 samples from the memory to the buffer even though the DMA limitation is just 1024?

Mohammad Arifur Rahman

↧
Viewing all 22218 articles
Browse latest View live
Search
<script src="https://jsc.adskeeper.com/r/s/rssing.com.1596347.js" async> </script>