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MSP430F5172: OOK modulation scheme: How best to implement this in MSP430F51** family?

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Part Number: MSP430F5172

Is there a way to implement an On-Off Keying modulation scheme using a module already existing within  this family of MCUs?  Alternately, are there any existing libraries that implement OOK already out there provided with Code Composer Studio which would work with this family of MCUs?

Specifically:   I have an external CMOS level reference clock @ 16MHz going into XT1 in High-Frequency, Bypass mode.   The 'sender' will be the MSP430 #1 driving an IR diode @ 56kHz, 50% duty cycle.   The 'receiver' will be a typical IR remote receiver such as any of Vishay's TSOP line; the receiver output goes into the input of another MSP430 (B)    These IR receivers use the modulated OOK signal @ 56kHz to reconstruct a data stream of some low bitrate -- a logic '1' when there is present the 56kHz carrier ... and a logic '0' in the absence of the same carrier.

I can think of ways to do this modulation using CCR's and timers, but it seems messy trying to roll a unique solution.  This topic is to discuss ways to implement OOK as described above by utilizing an existing module, or utilizing an ( unknown to me at this time ) existing library that implements the functionality.


CCS/MSP432P401R: How to configure ADC14, single channel, single conversion?

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Part Number: MSP432P401R

Tool/software: Code Composer Studio

Hello TI community 

I plan to convert the analog inputs of 5 sensors using ADC14. In other words, I want to put this task in a function, readADC, and whenever the program called it, five conversions are done. The ADC14 initiation is as follows:

void initADC(void)
{

P5SEL0 |= BIT1 + BIT2 + BIT3 + BIT4 + BIT5;  // ADC channels on A0, A1, A2,A3,A4
P5SEL1 |= BIT1 + BIT2 + BIT3 + BIT4 + BIT5;

ADC14->CTL0 = ADC14_CTL0_SHT0_1 | ADC14_CTL0_ON | ADC14_CTL0_SSEL_4 | ADC14_CTL0_CONSEQ_0 | ADC14_CTL0_SHP;
ADC14->CTL1 = ADC14_CTL1_RES_1; 

}

And also the conversions are done as follows:

void readADC(void)
{
/*************************************************************************************************/

ADC14->CTL0 &= ~(ADC14_CTL0_ENC|ADC14_CTL0_SC);
ADC14->MCTL[0] |= ADC14_MCTLN_INCH_0;
ADC14->CTL0 |= ADC14_CTL0_ENC |ADC14_CTL0_SC ;
while (ADC14->CTL0 == ADC14_CTL0_BUSY); // Wait if ADC14 core is active
sensor1= ADC14->MEM[0];
ADC14->CTL0 &= ~(ADC14_CTL0_ENC+ ADC14_CTL0_SC);
/*************************************************************************************************/
ADC14->MCTL[1] |= ADC14_MCTLN_INCH_1;
// ADC14->CTL1 |= ADC14_CTL1_CSTARTADD_1;
ADC14->CTL0 |= ADC14_CTL0_ENC |ADC14_CTL0_SC ;
while (ADC14->CTL0 == ADC14_CTL0_BUSY); // Wait if ADC14 core is active
sensor2= ADC14->MEM[1];
ADC14->CTL0 &= ~(ADC14_CTL0_ENC+ ADC14_CTL0_SC);
/*************************************************************************************************/
ADC14->MCTL[2] |= ADC14_MCTLN_INCH_2;
ADC14->CTL0 |= ADC14_CTL0_ENC |ADC14_CTL0_SC ;
while (ADC14->CTL0 == ADC14_CTL0_BUSY); // Wait if ADC14 core is active
sensor3= ADC14->MEM[2];
ADC14->CTL0 &= ~(ADC14_CTL0_ENC+ ADC14_CTL0_SC);
/*************************************************************************************************/
ADC14->MCTL[3] |= ADC14_MCTLN_INCH_3;
ADC14->CTL0 |= ADC14_CTL0_ENC |ADC14_CTL0_SC ;
while (ADC14->CTL0 == ADC14_CTL0_BUSY); // Wait if ADC14 core is active
sensor4= ADC14->MEM[3];
ADC14->CTL0 &= ~(ADC14_CTL0_ENC+ ADC14_CTL0_SC);
/*************************************************************************************************/
ADC14->MCTL[4] |= ADC14_MCTLN_INCH_4;
ADC14->CTL0 |= ADC14_CTL0_ENC |ADC14_CTL0_SC ;
while (ADC14->CTL0 == ADC14_CTL0_BUSY); // Wait if ADC14 core is active
sensor5= ADC14->MEM[5];
ADC14->CTL0 &= ~(ADC14_CTL0_ENC+ ADC14_CTL0_SC);
/*************************************************************************************************/
}

The problem I have is that the ADC14-> MEMx doesn't update and seems no conversions is done. Any idea where the problem is?

Thanks 

Saber

MSP432P4111: DMA from ADC and ability to gate MCLK again

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Part Number: MSP432P4111

Hi,

I wanted to clarify that when the DMA triggers and causes wake from LPM3 and enters LPM0

In all devices except MSP432P401R and MSP432P401M, wakeup from LPM3 or LPM4 modes upon DMA trigger from peripherals as well as external DMA trigger pin (DMAE0) is possible. It is necessary to configure the channel specific trigger source configuration registers in the DMA module for wake up from LPM3 or LPM4 modes in addition to configuring the peripherals or device pin for DMA trigger.

Device enters LPM0 mode upon wake up due to DMA triggers and DMA carries out the data transfer. CPU is inactive and remains in the clock gated state. Device remains in LPM0 itself after DMA transfers are completed. Device can go into active mode either upon DMA DONE interrupt condition or upon other peripheral/pin interrupts. If re-entry into LPM3 or LPM4 is desired, then sleep-on-exit may be programmed in the Arm core and LPM3 or LPM4 mode will be restored after ISR execution is completed.

Does this mean that when the DMA completes a transfer from ADC to memory and waits for the next sample from the ADC, that the MCU does not gate MCLK and enter LPM3?

We are looking for lowest power operation of ADC + DMA to collect a number of samples before turning on the ARM core, and during that time we are looking for a way to enable and gate MCLK to the DMA.

What is the lowest power scheme of doing this on the MSP432P4111?

Regards,

--Gunter

MSP430F2013: Unexpected resets during I2C transfer after flash erase

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Part Number: MSP430F2013

I have a custom bootloader communicating with the host using I2C and running in FC00-FFFF address space. I2C slave is interrupt driven. To program flash, an I2C command is send to erase the application space F800-FBFF. Before executing ERASE command the code verifies that the application space has non-0xFFFF words in it. If non-0xFFFF word is found, the sector is erased and the following sector is checked for non-0xFFF words. Since erasing is executed from ISR, I2C bus is released after the flash is erased thus preventing the host from sending the next command.

After the flash is erased and USIIFG flag is cleared releasing I2C bus, the host issues commands to program flash, 8 word (16 bytes) in one I2C transfer. After the last byte of the command is received and before the ACk bit is sent back to the master, the flash is programmed. After programming I2C bus is released, ready to receive the next segment of data.

What I have noticed is during I2C transfer the micro appears to jump to a reset vector around the time of a USI interrupt.

In the diagram above, P1.4 and P1.5 are toggled at the same inside an USI ISR when start condition is detected. P1.5 by itself is toggled as the first instruction after reset inside _c_int00() before the stack pointer is loaded. P1.4 is toggled as the first instruction inside my USI ISR and it is also toggled when the bits are successfully processed and USI is ready for the next transfer. In the middle of the diagram you can see P1.5 toggle by itself when indicates that my MCU started executing from a reset vector. About 0.1ms before that you can see line P1.4 toggle twice, first time when the USI isr begins to execute at the second time when the bit counter in USI controller is loaded to receive the next 8 bits. After the 8 bits arrive, no interrupt is generated and I2C bus is not held low. But instead, the MCU starts executing from reset vector. It is important to note that "reset" occurs during I2C transfer long before all 16 bytes of data are received and "flash write" is executed. Some times it occurs when receiving I2C address byte.

However, if MCU is programmed with only my bootloader (application address space 0xF800-FBFF is all 0xFFs), when "erase flash" command is received from the host, erasing does not executed because all bytes are already at 0xFF. After that, all I2C transfers to program flash occur without "resets".

Somehow, erasing flash causes USI interrupts (those interrupts occur much later) to misfire causing MCU to start from a reset vector. However, programming flash does not affect USI interrupts and the appplication is successfully loaded. One average, about 13 I2C transfers are succeed programming 13*16 = 208 bytes before a "restart" occurs resulting in failed I2C transfer (NACK received).

The watchdog is disabled right after SP is initialized. No other interrupts are enabled and NMI interrupt is pointing to a reset trap (infinite loop). What could cause the MCU to execute from a reset vector?

Thanks

MSP430FR5994: Main Memory Boot Loader for downloading any code

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Part Number: MSP430FR5994

                Main Memory BootLoader FRAM

 

Dear Sirs:

     Am I completely missing the point of the MMBL (FRAM) example?

     Can I use this example to download my own code by first running the compiler generated .hex

file through the perl scripter and then downloading it into my system using an eval board?

 

Thanks,

John

CCS/MSP432P401R: TimerTA0_0 interrupt goes to infinite loop (exit.c)!

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Part Number: MSP432P401R

Tool/software: Code Composer Studio

Hello TI community

I plan to use timerA interrupt to toggle two LEDs at 44.1 kHz. But when I run my program, it goes to exit.c. Below is my code:

/********************************************************************************************************************************/

WDT_A->CTL = WDT_A_CTL_PW | WDT_A_CTL_HOLD; // stop watchdog timer


P2DIR |=BIT2+BIT1;  //LEDs
P2OUT |= (BIT1+BIT2);//LEDs

/***************************Configure Timer****************************************************************/

TIMER_A0->CCTL[0] = TIMER_A_CCTLN_CCIE; //Enable CC interrupt

TIMER_A0->CTL = TIMER_A_CTL_TASSEL_2 | //Select SMCLK as source for timer
TIMER_A_CTL_ID_3 | //Divide clock by 8 (this yields 6 MHz for the timer clock)
TIMER_A_CTL_MC_1 | //Up mode
TIMER_A_CTL_CLR ; //Clear timer count

TIMER_A0->CCR[0] = 136; // 6 MHz / 44.1 kHz = 136
// __enable_irq();
__enable_interrupt();


}
void TA0_0_IRQHandler(void)
{
P2->OUT ^= (BIT2+BIT1);

}

Any idea where the problem is?

Thanks

Saber

MSP430FR6877: UCTXSTT bit is not generated

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Part Number: MSP430FR6877

Hello experts,

 My customer have question for UCTXSTT bit and UCTXIFG bit.

 Due to electrostatic noise, UCTXIFG bit is not generated after UCTXSTT bit.

 Is there good way to solve this problem? Timeout processing can be one way to solve this problem?

Thank you for your cooperation.

Thanks and best regards,

Ryo Akashi

MSP430F2132: What it the MSP430F2132 BSL pin ? uart or pin 1.1/1.2?Tks!

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Part Number: MSP430F2132

Dears,

What it  the MSP430F2132 BSL pin ? uart (pin3.4/pin3.5)or  pin 1.1/ pin1.2?Tks!


CCS/MSP430FR2355: CCS/MSP430FR2355

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Part Number: MSP430FR2355

Tool/software: Code Composer Studio

 In the given program the clock is taken from the external crystal where P2.6 and P2.7 assigned as XIN and XOUT pins of the crystal respectively.So according to me the frequency is decided by the crystal then how TBSSEL_x of the  TB0CTL register are controlling the frequency of the the clock.
#include <msp430.h>

int main(void)
{
    WDTCTL = WDTPW | WDTHOLD;                         // Stop WDT

    // Configure GPIO
    P1DIR |= BIT6 | BIT7;                             // P1.6 and P1.7 output
    P1SEL1 |= BIT6 | BIT7;                            // P1.6 and P1.7 options select
    P2SEL1 |= BIT6 | BIT7;                            // P2.6~P2.7: crystal pins
    do
    {
        CSCTL7 &= ~(XT1OFFG | DCOFFG);                // Clear XT1 and DCO fault flag
        SFRIFG1 &= ~OFIFG;
    }while (SFRIFG1 & OFIFG);                         // Test oscillator fault flag
    // Disable the GPIO power-on default high-impedance mode to activate
    // previously configured port settings
    PM5CTL0 &= ~LOCKLPM5;

    // Setup Timer0_B
    TB0CCR0 = 100-1;                                  // PWM Period
    TB0CCTL1 = OUTMOD_7;                              // CCR1 reset/set
    TB0CCR1 = 75;                                     // CCR1 PWM duty cycle
    TB0CCTL2 = OUTMOD_7;                              // CCR2 reset/set
    TB0CCR2 = 25;                                     // CCR2 PWM duty cycle
    TB0CTL = TBSSEL_1 | MC_1 | TBCLR;                 // ACLK, up mode, clear TBR

    __bis_SR_register(LPM3_bits);                     // Enter LPM3
    __no_operation();                                 // For debug
}

MSP430F2002: Sporadic abormal CPU behaviour after PON

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Part Number: MSP430F2002

Hi champs,

after startup MCU sometimes shows a non expected behaviour (try to get more information from customer).

During this abnormal state, power consumption is significant lower (my not confirmed assumption: CPU clock is much lower than expected).

This behaviour can only be seen without JTAG debugger!

CLK is configured at beginning of code. A workaround seems to insert 2 x __no_operation() to bypass tis behaviour.

Only one __no_operation()  does not work secureley!

Customer thought erratum BCL12 can be applied, but code is executed after PON, so very unlikely.

Here is code sequence:

  /* Set the MCLK to 12MHz calibrated */

  DCOCTL = 0;                /* Select lowest DCOx and MODx settings */

  BCSCTL1 = CALBC1_12MHZ;    /* Set range */

  DCOCTL = CALDCO_12MHZ;     /* Set DCO step + modulation */

  BCSCTL2 |= DIVS_2;         /* SMCLK = 3 MHz */

  __no_operation();

  __no_operation();

 

Q: Why are 2 x __no_operation() needed and is this a valid workaround  to ensure stable execution in mass production ?

 

 

CCS/MSP430F5529: USB Low Power lock

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Part Number: MSP430F5529

Tool/software: Code Composer Studio

Hi 

I am trialling the USB code that is bundled with the Launchpad for the MSP430F5529 and have compiled using the CDC. The device runs fine and communicates perfectly, however it goes into Low Power mode sometime after the PC enters sleep. The USB serial port is then switched off on the PC, and one cannot re-start the microcontroller from the USB - a reset of the MSP430 is required. I have edited all the functions in usbEventHandling.c to return TRUE but this does not fix the issue. I have also tried removing the bWake condition in iUsbInterruptHandler(void) in usblsr.c to always clear the low power mode bits (see below) but this also does not work.

//if (bWakeUp) //wdm change
    //{
        __bic_SR_register_on_exit(LPM3_bits);   // Exit LPM0-3
        __no_operation();  // Required for debugger
    //}

Please can you assist?

Regards, Warren

MSP430FG6626: MCU with USB HOST or OTG interface

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Part Number: MSP430FG6626

Hi sirs,

Do you have MSP430FG6626 similar MCU with USB HOST or OTG interface?

Application: Blood glucose machine

MSP430F6736: MSP430F6736 AUX Issue

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Part Number: MSP430F6736

AUX1,AUX2 are used for voltage detection.DVCC voltage is 3.3v, AUX voltage detection threshold is 2.4v, but the actual AUX power voltage is 3.6v or 3.8v, what's wrong with it?

CCS/MSP-EXP430F5529: Toggle Rate Of GPIO

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Part Number: MSP-EXP430F5529

Tool/software: Code Composer Studio

Hello everyone,

I have a simple question regarding the toggle rate of any GPIO.

Suppose i set my 5529 to operate at 25Mhz by setting DCO, now i toggle any pin of my controller like this.

P2DIR |= BIT2;

while(1)

{

P2OUT |= BIT2;

P2OUT &=~ BIT2;

so i got a square wave on P2.2 of approx 2.3 Mhz.

My question is that if i set DCO at 25 Mhz then why my P2.2 cannot toggle at same rate?

and why it shows 2.3 Mhz?

I want maximum toggling rate of my GPIO for my Project.

Please give me any suggestion.

CCS/MSP430FR2355: CCS/MSP430FR2355

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Part Number: MSP430FR2355

Tool/software: Code Composer Studio

#include <msp430.h>

int main(void)
{
  WDTCTL = WDTPW | WDTHOLD;                 // Stop WDT
  
  // Configure GPIO
  P1DIR |= BIT0;
  P1OUT = 0;
  
  P2SEL0 |= BIT7;                           // P2.7 selected as TB0CLK

  // Disable the GPIO power-on default high-impedance mode to activate
  // previously configured port settings
  PM5CTL0 &= ~LOCKLPM5;

  // Configure Timer_B
  TB0CTL = TBSSEL_0 | MC_2 | TBCLR | TBIE;  // ACLK, count mode, clear TBR, enable interrupt
  TB0R = 0xFFFF - 20;                       // Offset until TBR overflow
  __bis_SR_register(LPM4_bits | GIE);       // Enter LPM4, enable interrupts
  __no_operation();                         // For debug

  while (1)
  {
    P1OUT ^= BIT0;                          // P1.0 = toggle
    __bis_SR_register(LPM0_bits);           // CPU is not required
  }
}

// Timer0_B3 Interrupt Vector (TBIV) handler
#if defined(__TI_COMPILER_VERSION__) || defined(__IAR_SYSTEMS_ICC__)
#pragma vector=TIMER0_B1_VECTOR
__interrupt void TIMER0_B1_ISR(void)
#elif defined(__GNUC__)
void __attribute__ ((interrupt(TIMER0_B1_VECTOR))) TIMER0_B1_ISR (void)
#else
#error Compiler not supported!
#endif
{
  switch(__even_in_range(TB0IV,TB0IV_TBIFG))
  {
      case TB0IV_NONE:
          break;                             // No interrupt
      case TB0IV_TBCCR1:
          break;                             // CCR1 not used
      case TB0IV_TBCCR2:
          TB0CCR2 += 50000;                  // Add Offset to TBCCR1
          __bic_SR_register_on_exit(LPM0_bits);// CPU active on reti
          break;                             // CCR2 not used
      case TB0IV_TBIFG:                      // overflow
          TB0CTL = TBSSEL_2 | TBCLR;         // SMCLK, clear TBR
          TB0CCTL2 = CCIE;                   // TBCCR1 interrupt enabled
          TB0CCR2 = 50000;
          TB0CTL |= MC_2;                    // Start Timer_B in continuous
          __bic_SR_register_on_exit(LPM4_bits);// Exit LPM4 on reti
          break;
      default:
          break;
  }
}

In this program there are several things that I am not able to understand:

1. P1.0 LED   toggle  every 50000 SMCLK cycles.How this LED is controlled by interrupt so that there is delay of 50000 .

2. TB0R = 0xFFFF - 20; What is the meaning of this line of the code?

Since TB0R counts from 0 to 65535 but after this statement what are happening in this program?As per the code TAIFG will be generated and this interrupt initiate SMCLK and clear TB0R and timer is in the stop mode and in the next line of the code CCIFG is enabled when count reaches to 50000.

TB0CCTL2 = CCIE;


TB0CCR2 = 50000;

Afterward timer starts in the continuous mode by this line

TB0CTL |= MC_2; 

After execution of these statement CCIFG initiate  another ISR:-

case TB0IV_TBCCR2

TB0CCR2 += 50000; // Add Offset to TBCCR1

__bic_SR_register_on_exit(LPM0_bits);
break; 

But how these code are controlling the LED which is beyond my understanding.My question may be sound like silly since I have just started to learn so sorry for that and please help me to understand this logic.


CCS: MSP430FR5887 ESI

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Tool/software: Code Composer Studio

//User need to switch on the motor with half-covered matal disc to finish the calibration
Set_DAC();
Is there any requirement for the speed of the dial to calibrate the DAC when the dial rotates? If so, what is the speed.

CCS/MSP430FR6972: MSP430FR6972 can you provide the AES function sample code?

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Part Number: MSP430FR6972

Tool/software: Code Composer Studio

MSP430FR6972 can you provide the AES function sample code?

CCS/MSP430I2040: MSP430i2040

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Part Number: MSP430I2040

Tool/software: Code Composer Studio

Hello,

We are planning to refer design of MSP 430i2040 Submeter EVM ver 1.2 for our application.

In CD received along with EVM module, hardware details are available (Schematics, layout etc) but software(EVM library) files are not there.

From where I can get this EVM library ?

Or is  sample code available on website for EVM? Is this code easy to modify as per our application( like integrate code to generate PWM signal, change in serial protocol (for sending metering parameters) as per application.

Please guide me how to proceed to get result fast.

Thanks,

Anuradha.

CCS/MSP-EXP430FR5969: Support on UART Debug for left & Right J4 & J5 in EXP-MSP430FR5969

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Part Number: MSP-EXP430FR5969

Tool/software: Code Composer Studio

Hi Team,

I am able to access the J13 RXD & TXD command status through terminal port

now need the support on the Left & Right TXD & RXD communication

please help on this request

Regards,

Chandrasekaran V

MSP432E401Y: MSP432E401Y: Running SimpleLink MSP432E4 SDK (MSP432E4 DriverLib 1.10.00.01) on Keil uVision

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Part Number: MSP432E401Y

Hello I installed TI MSP432E4_DFP package via Pack Installer on uVision (Version 5.25.2.0) and the simplelink MSP432E4 SDK like description on quick start manual. I got no errors and it seems to be fine But after opening any simplelink SDK uVison Keil example project (for example: ti\simplelink_msp432e4_sdk_3_20_00_10\examples\nortos\MSP_EXP432E401Y\driverlib\empty\keil) I got the following building error: "L6024U: Library msp432e4_driverlib.a contains an invalid member Name". What could be the Problem?

When I use instead the same example project for CCS in CCS v9.1 (for example: ti\simplelink_msp432e4_sdk_3_20_00_10\examples\nortos\MSP_EXP432E401Y\driverlib\empty\ccs) everthing works fine, no building problems?

Maybe the driver lib for keil (ti\simplelink_msp432e4_sdk_3_20_00_10\source\ti\devices\msp432e4\driverlib\lib\keil\m4f) is not working? Or is it because I'm using TexasInstruments.MSP432E4_DFP.3.2.6.pack not TexasInstruments.MSP432E4_DFP.3.1.0.pack?

Greetings

Manfred

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