MSP432P4111: Store redundant copies of firmware image in two separate location in flash main memory

April 25, 2019, 12:14 am

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Part Number:MSP432P4111

Hi,

Wanted to know if it is possible to store output image to two separate location in Main memory

MEMORY
{
    FLASH1    (RX) : origin = 0x00000000, length = 0x00100000
    FLASH2    (RX) : origin = 0x00100000, length = 0x00100000
    INFO         (RX) : origin = 0x00200000, length = 0x00008000
    ALIAS
    {
    SRAM_CODE  (RWX): origin = 0x01000000
    SRAM_DATA  (RW) : origin = 0x20000000
    } length = 0x00040000
}

/* Section allocation in memory */

SECTIONS
{


    .text       : {}   >> FLASH1 | FLASH2
    .const      : {}   >> FLASH1 | FLASH2
    .cinit      : {}   >> FLASH1 | FLASH2
    .pinit      : {}   >> FLASH1 | FLASH2
    .init_array : {}   >> FLASH1 | FLASH2

.....
.....
}

This is the current memory layout I have, I want the FLASH2 Area should also get populated with the same data as FLASH1

Thanks

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CCS/MSP432P401R: MSP432P401R

April 25, 2019, 12:51 am

≫ Next: RTOS/MSP432E401Y: GPIO_setCallback responding issue

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Part Number:MSP432P401R

Tool/software: Code Composer Studio

Hello sir, i have to select microcontroller for portable battery power medical deivece.for that  i m looking for  a microcontroller with 16 bit SAR ADC with 1 MSPS and built in BLE Hardware. SO, please suggest me.

is there any MSP microcontroller comes with built in BLE Hardware?

RTOS/MSP432E401Y: GPIO_setCallback responding issue

April 25, 2019, 1:23 am

≫ Next: MSP-EXP430FR2433: Port characteristic difference btw P1.5 and P2.7 with driverlib

≪ Previous: CCS/MSP432P401R: MSP432P401R

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Part Number:MSP432E401Y

Tool/software: TI-RTOS

Hi,

In my application i have to use some gpio's whcih are inputs to the controller and controlled externally with momentary switches.

Based on the switch control i have to send some data over uart.

I have chosen "gpiointerrupt" example for my application.

In the callback function i have written:

void gpio_switch_Fxn(unsigned int index)

{

uart_write(uart,&Tx_Data,sizeof(Tx_Data));

}

Issues:

Initially when i hold the external switch,

1.         Data on uart is transmitting however which is not continuous. I have to send the continuous data while holding the switch after releasing no transmission. But it is not happening.

             If i release the switch and again if i hold transmission takes place but that is for just a second.

2.         One more thing is that, when  i am repeating this activity holding and releasing the switch - after some time transmission stops. No data one uart (unlike initial).

Can anyone help me on this.

Thank you

Regards

Kalyan,

MSP-EXP430FR2433: Port characteristic difference btw P1.5 and P2.7 with driverlib

April 25, 2019, 2:55 am

≫ Next: encoder interface with msp430f5529

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Part Number:MSP-EXP430FR2433

Hello All!

I am building a simple SSD1306 OLED library on MSP-EXP430FR2433 Launchpad. I am using SPI as serial communication interface.

I made it run and development was going well until I faced a weird issue with P2.7

I was using P1.5 for RESET signal of SPI SSD1306 OLED controller. Then I needed to use that pin for UART RX functionality on eUSCIA0. So I changed the reset signal to P2.7 pin. Right after this, I cannot get image on my OLED display. The reset signal is ONLY used in initialization section routine of my library. And the weird thing, if I change the RESET line back to P1.5, bingo it works again.

I checked the datasheet to see some difference btw P1.5 and P2.7, could not find any. Also I connected P2.7 to onboard led with a jumper wire, port seems functioning because led responds as I expect.

I use CCS cloud ide, so compiler version and driverlib version is the default ones on cloud.

Thanks in advance!

encoder interface with msp430f5529

April 25, 2019, 5:03 am

≫ Next: MSP432P401R: MSP432, ADC power consumption

≪ Previous: MSP-EXP430FR2433: Port characteristic difference btw P1.5 and P2.7 with driverlib

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Dear Sir,

         how to encoder interface with msp430f5529.

         

MSP432P401R: MSP432, ADC power consumption

April 25, 2019, 5:22 am

≫ Next: MSP430FR6043: Optimised library gives Alg. error 123

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Part Number:MSP432P401R

Hi Team,

My customer is using MSP432 in BBU projects, here are some questions about the Vref of ADC, could you share some comments, thanks.

1. Do you have any words about power consumption, temperature coefficient, accuracy of the internal Vref (3 level: 1.2V, 1.45V, 2.5V).
2. Which pin the provide the power to the internal Vref, AVCC or DVCC or any other pin?
3. If using the external Vref (AVCC or VREF+), is there any difference between them in power consumer, temperature coefficient, accuracy?
4. How about the max power consumer of the ADC, 875uA?

MSP430FR6043: Optimised library gives Alg. error 123

April 25, 2019, 9:36 am

≫ Next: MSP430F5438A: Problem with stat crystal (XT1,XT2) on MSP430F5438A

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Part Number:MSP430FR6043

Hi,

When I switch to the optimised library (version 02_20_00_16) option Lobe, I get error USS_message_code_algorithm_error (123) after measuring flow. With the full library everything works fine without errors. Is there a reson for this?

Thanks in advance!

Thibault 

MSP430F5438A: Problem with stat crystal (XT1,XT2) on MSP430F5438A

April 25, 2019, 10:40 am

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Part Number:MSP430F5438A

Hello everyone,
I started to learn about MSP430F5438A, I have a problem with starting the clock. I have attached the circuit board schematics file I designed. 

The schematic of the entire circuit board can be viewed in this link driver:

drive.google.com/.../view

I downloaded the example code about msp430x54xA_UCS_6.c in this link.

http://dev.ti.com/tirex/explore/node?node=AMtL227pGhUpuFnMS3tjJQ__IOGqZri__LATEST

The compiler I use is IAR for MSP430 version 7.12.
Using the debug feature, I noticed that my program was running forever in the do while loop.

There is an absurdity here I cannot understand.

#define DCOFFG (0x0001u) / * DCO Fault Flag * /
#define XT1LFOFFG (0x0002u) / * XT1 Low Frequency * /
#define XT1HFOFFG (0x0004u) / * XT1 High Frequency * /
#define XT2OFFG (0x0008u) / * High Frequency Oscillator 2 * /

The initial value of UCSCTL7 = 1027 (0b0000 0100 0000 0011) when I open the debug program.

I think, after the command
UCSCTL7 & = ~ (XT2OFFG + XT1LFOFFG + XT1HFOFFG + DCOFFG);
The value of UCSCTL7 = 1024 (0b0000 0100 0000 0000), but it gives a value of 1026 (0b0000 0100 0000 0010). This makes the do while loop run forever.

Can someone explain help me with.
Thanks guys so much.

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Compiler/MSP432P401R: BSL build issue

April 25, 2019, 12:32 pm

≫ Next: MSP432E411Y-BGAEVM: MSP432E411

≪ Previous: MSP430F5438A: Problem with stat crystal (XT1,XT2) on MSP430F5438A

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Part Number:MSP432P401R

Tool/software: TI C/C++ Compiler

Dear forum!

I think I have a compiler, build system or project settings issue, when trying to build the MSP432 BSL,
while using a newer toolchain than the one having being used with the latest BSL available on TIs site.

I need to customize the BSL for the MSP432P401R.

So I tried to follow the "MSP432P4xx SimpleLink™ Microcontrollers Bootloader" documentation "slau622h.pdf".
Read chapter 5,  "Reprogram and Customize the BSL".
Downloaded the source archive MSP432BSL_1_01_00_00.zip, followed the instructions,
built the BSL using Code Composer Studio  8.1.0.00011 (recent updates).

I flashed the resulting image "BSL432_MSP432P401x.out" onto a MSP-EXP432P401R Rev. 2.1 board,
again following the instructions from the PDF mentioned above.

The resulting image doesn't work properly. E.g. sending a wrong password does not erase the flash memory.

I reflashed the original BSL image (also inside the archive mentioned above), and this BSL behaves as it should.

I compared the .map files and see quite some differences, though I'm not really sure what to look for.

The original BSL seems to have been built with e.g. the "TI ARM Linker PC v15.12.3", while my installation uses the "TI ARM Linker PC v18.1.2".

I tried to debug the resulting BSL version in FLASH (Release), and it seems to work partially.
E.g. I can see the initial "BSL432_RX_PASSWORD" together with the transmitted password and message framing inside the
BSL432_ReceiveBuffer, but then the CPU reads a false value 0x20 instead of 0x21 in:

void BSL432_CI_interpretCommand()
{
    uint8_t command = BSL432_ReceiveBuffer[3];

into reg3, but that might be some debugging problems trying non debug code running from FLASH/SRAM with the XDS110-ET?

So could please someone shed some light on what's going wrong here?
And possibly verify the BSL is building fine with recent CCS/compiler toolchain versions?
Do I need to rebuild the DriverLib as well?

Thank you very much in advance
BR
 Hawk
 
PS: I'm not sure if this matters: I'm using software invocation of the BSL and I2C as the BSL interface
#define BSL_PARAM 0xFC48FFFF // I2C slave address = 0x48, Interface selection = Auto

(Please visit the site to view this file)(Please visit the site to view this file)

MSP432E411Y-BGAEVM: MSP432E411

April 25, 2019, 1:12 pm

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Part Number:MSP432E411Y-BGAEVM

In the technical reference for MSP432 LCD controller is note like this:

NOTE: When using the LCD with EPI to interface to external memory, the external code address
space 0x1000.0000 must be selected by programing the ECADR field to 0x1 in the EPI
Address Map (EPIADDRMAP) register at EPI offset 0x01C.

Does anyone know why is it? I am using external SDRAM connected to EPI interface and I only need to program ram space and size - for the space 0x6000.0000.and for normal read/write operations it works. I do not understand previous note about ECADR field.

Thanks for answer.

MSP430G2553: I can't set period of PWM signal

April 25, 2019, 1:52 pm

≫ Next: MSP432E401Y: ADC does not read from PK0-3 (AIN16-19)

≪ Previous: MSP432E411Y-BGAEVM: MSP432E411

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Part Number:MSP430G2553

Hi,

i would like to create a PWM signal. And i want the frequency to be close to 38 khz. My theoretical calculation for period is 26.3 microseconds. So i choose 26 microseconds. And i can observe my signal. 

But i don't understand how my code works properly :)

(My clock frequency is 1MHz so my clock signal period is 1 microseconds )

if((P1IN & BIT3)!=BIT3)  { // if button is pressed

for(i=0;i<692;i++){   // pwm signal's duration is 9ms
P2OUT^=0x01;       // switch from 1 to 0 or vice versa
__delay_cycles(4);   
}
P2OUT=0x00;
}

my calculation is:

 <692,i++,P2OUT^=0x01; //   total 3 cycles

  __delay_cycles(4); //total 4 cycles 

so 4+3=7.  but i'm confused because i think it should be 13 not 7

MSP432E401Y: ADC does not read from PK0-3 (AIN16-19)

April 25, 2019, 1:54 pm

≫ Next: CCS/MSP430F2013: Wrong result on int16 math

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Part Number:MSP432E401Y

There is an ADC tutorial at:
dev.ti.com/.../msp432e4_ADCBuf.html
It starts with the adcbufmultisequencer_MSP_EXP432E401Y_tirtos_ccs example and applies a few modifications.  I carried it through step 4 "Running the starter example" and proceeded to test it by applying voltages at "Board_ADCBUF0CHANNEL0" and "Board_ADCBUF0CHANNEL1", which resolve to pins "PE3" and "PE2" (via the adcBuf0MSP432E4Channels[] array in MSP_EXP432E401Y.c).  To the ADC these pins become "AIN0" and "AIN1".  Viewing the console output the testing works as expected, where the numbers being outputted were 0 or nearly 0 when the input is grounded, and (nearly) 4095 when 3.3V is applied.

Then I tried to test the other ADC inputs.  This is done by modifying the first two entries of the adcBuf0MSP432E4Channels[] array in MSP_EXP432E401Y.c.  Channels AIN0 through AIN15 work as expected, but channels AIN16 - AIN19 (PK0 - PK3) are ignored!  No changes in these last 4 inputs are reflected in the numbers being outputted!  Why?  What must be done so that the ADC will see these?

Brian S

CCS/MSP430F2013: Wrong result on int16 math

April 25, 2019, 2:05 pm

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Part Number:MSP430F2013

Tool/software: Code Composer Studio

Hi,

I wrote a function to remove an offset from a sample and saturate it if the operation extrapolates the int16 range.

However, apparently when the result off subtraction is "-1" there are some weird behaviors returning "-255", "-256", "255" or "256".

If the offset is sufficient to the result be completely positive or negative there are no spikes (second half of plot).

During the test, I noted that this behavior happens inside the "else" precisely when there is no saturation happening, but there is something affecting the result of subtraction. Other weird behavior is that I can't trigger this behavior inside debugger (running line by line or even putting an "if (sub < -100)" to halt the execution).

I tested the same function (code) on Arduino: Receive the data with offset and then remove it, and there are no spikes.

What is the problem?

EVM430-FR6047: Problem with debugging and uploading firmware

April 25, 2019, 3:27 pm

≫ Next: CCS/MSP430FR2355: The minimal time to execute the interrupt in MSP430

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Part Number:EVM430-FR6047

Hello,
I tried to reupload the original firmware to the EVM430-FR6047, but when I connect to the GUI, the following message appear: HID Bridge connected - waiting for device. Therefore, the firmware might not be uploaded correctly right? Here are the jumpers connections:

I'm trying to upload the firmware using the UniFlash connecting the MSP430FR6047 on chip, loading the image that's in the following folder:
C:\ti\msp\UltrasonicWaterFR604x_02_20_00_04\image
It seems it's working:


What am I doing wrong? How can I upload the firmware properly?

Thanks in advance

CCS/MSP430FR2355: The minimal time to execute the interrupt in MSP430

April 25, 2019, 4:24 pm

≫ Next: CCS/EVM430-F6779: Load and run the EMDC generated firmware using the CCS IDE

≪ Previous: EVM430-FR6047: Problem with debugging and uploading firmware

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Part Number:MSP430FR2355

Tool/software: Code Composer Studio

Hi,

  I'm currently using the MSP430FR2355.

  I use an external clock to trigger the pin interrupt in the MSP430. The external clock is about 9.6kHz which is about 104 microsecond.

  I'm looking the wave in the oscilloscope, the clock is right. But it seems that the interrupt is not triggered every clock cycle.

  So I wonder if the 104 microsecond is too fast for MSP430 to execute the interrupt. And normally how long does the MSP430FR2355 enter and exit of the interrupt.

  If anyone can help, I will be so grateful.

Sincerely,

Jiangang

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CCS/EVM430-F6779: Load and run the EMDC generated firmware using the CCS IDE

April 25, 2019, 10:53 pm

≫ Next: RTOS/MSP432E401Y: Compilation Error while creating new TI RTOS based project for msp432e401y

≪ Previous: CCS/MSP430FR2355: The minimal time to execute the interrupt in MSP430

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Part Number:EVM430-F6779

Tool/software: Code Composer Studio

Hello,

After importing EMDC generated Source code into CCS v8, click the debugger icon to build and download the code to the target. Then start the code by clicking the run button. Then click stop debugging and power cycle the target. why don't we use release mode instead of debugger icon to build and download the code to the target?

RTOS/MSP432E401Y: Compilation Error while creating new TI RTOS based project for msp432e401y

April 25, 2019, 11:16 pm

≫ Next: MSP430FR6047: measuring integrated flow

≪ Previous: CCS/EVM430-F6779: Load and run the EMDC generated firmware using the CCS IDE

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Part Number:MSP432E401Y

Tool/software: TI-RTOS

Hi All,

I have MSP-EXP432E401Y evaluation board and I tried to run sample code on this and it works fine.

Now I am trying to create one new RTOS based project in CCS Version: 8.3.0.00009 , xdctool "xdctools_3_51_02_21_core", and "tirtos_msp43x_2_20_00_06".

I have referred "TI-RTOS Kernel (SYS/BIOS) User's Guide" document (Section 2) for creating new project. But I am getting below error while building project, any help will be appreciated...

**** Build of configuration Debug for project aaa ****

"C:\\ti\\ccsv8\\utils\\bin\\gmake" -k -j 4 all -O

Building file: "../aaa.cfg"
Invoking: XDCtools
"C:/ti/xdctools_3_51_02_21_core/xs" --xdcpath="C:/ti/simplelink_msp432e4_sdk_3_10_00_11/source;C:/ti/simplelink_msp432e4_sdk_3_10_00_11/kernel/tirtos/packages;" xdc.tools.configuro -o configPkg -t ti.targets.arm.elf.M4F -p ti.platforms.msp432:MSP432E401Y -r debug -c "C:/ti/ccsv8/tools/compiler/ti-cgt-arm_18.1.4.LTS" "../aaa.cfg"
configuring aaa.xem4f from package/cfg/aaa_pem4f.cfg ...
subdir_rules.mk:12: recipe for target 'build-1718179921-inproc' failed
js: "C:/ti/simplelink_msp432e4_sdk_3_10_00_11/kernel/tirtos/packages/ti/targets/linkUtils.xs", line 84: xdc.services.global.XDCException: xdc.FILE_NOT_FOUND: can't locate file 'ti/targets/rts6000/link.xdt' along the path: C:\ti\simplelink_msp432e4_sdk_3_10_00_11\kernel\tirtos\packages\ti\platforms\msp432;C:/ti/simplelink_msp432e4_sdk_3_10_00_11/source;C:/ti/simplelink_msp432e4_sdk_3_10_00_11/kernel/tirtos/packages;C:/ti/xdctools_3_51_02_21_core/packages;..;
"C:/ti/simplelink_msp432e4_sdk_3_10_00_11/kernel/tirtos/packages/ti/platforms/msp432/linkcmd.xdt#93(eval)", line 1
"C:/ti/simplelink_msp432e4_sdk_3_10_00_11/kernel/tirtos/packages/ti/platforms/msp432/linkcmd.xdt", line 93
"C:/ti/simplelink_msp432e4_sdk_3_10_00_11/kernel/tirtos/packages/ti/platforms/msp432/linkcmd.xdt", line 134
xdctools_3_51_02_21_core\gmake.exe: *** [package.mak:202: package/cfg/aaa_pem4f.xdl] Error 1
xdctools_3_51_02_21_core\gmake.exe: *** Deleting file 'package/cfg/aaa_pem4f.xdl'
xdctools_3_51_02_21_core\gmake.exe: *** [package/cfg/aaa_pem4f.xdl] Deleting file 'package/cfg/aaa_pem4f.h'
xdctools_3_51_02_21_core\gmake.exe: *** [package/cfg/aaa_pem4f.xdl] Deleting file 'package/cfg/aaa_pem4f.c'
js: "C:/ti/xdctools_3_51_02_21_core/packages/xdc/tools/Cmdr.xs", line 52: Error: xdc.tools.configuro: configuration failed due to earlier errors (status = 2); 'linker.cmd' deleted.
gmake[1]: *** [build-1718179921-inproc] Error 1
subdir_rules.mk:9: recipe for target 'build-1718179921' failed
gmake: *** [build-1718179921] Error 2
gmake: Target 'all' not remade because of errors.

**** Build Finished ****

MSP430FR6047: measuring integrated flow

April 26, 2019, 1:09 am

≫ Next: MSP432P401R: "Information Memory" partition missing

≪ Previous: RTOS/MSP432E401Y: Compilation Error while creating new TI RTOS based project for msp432e401y

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Part Number:MSP430FR6047

Hello!

I have a question of calculating integrated flow.

1. We can set parameter of UPS0 to UPS1 Gap, but after I generate headers, I cannot find it in code.

 So please let me know the parameter name in code.

2. After logging, I open the file and there is a time stamp.

If I set UPS0 to UPS1 Gap  as 200ms, but the time stamp between delta tof if not 200ms, some of 200ms, and some of 190ms.

So I wonder the gap of result value is 200ms or not.

3. Is there to get integrated flow?

Thanks.

MSP432P401R: "Information Memory" partition missing

April 26, 2019, 1:59 am

≫ Next: CCS/MSP430FR6989: USCI_A1_SPI_MODE Master Receive with DMA Problem

≪ Previous: MSP430FR6047: measuring integrated flow

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Part Number:MSP432P401R

Hello,

I bough several MSP432P401RIPZR from mouser.com and placed to my custom PCB.

When I try flash it via J-Link or XDS110, SWD interface, operation crash on command "g_DeviceID   = __readMemory32(0x0020100C, "Memory");".

I can read chip memory via segger JMem.exe, but "Information Memory" partition on adress 0x0020000 to 0x00203FFF is missing, it is like hardware part of memory is missing, rest of memory I can read without problems. Same behavior shows via XDS110 and IAR debug. All chips I bough have same behavior.

What do you thing? Are chips broken or I missed some crucial step in flash process? What can I try next?

Best regards

Michal
 

CCS/MSP430FR6989: USCI_A1_SPI_MODE Master Receive with DMA Problem

April 26, 2019, 2:02 am

≫ Next: MSP430F6736A: voltage at RST pin less than AVCC

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Part Number:MSP430FR6989

Tool/software: Code Composer Studio

Hello Community.

I have Usci A1 in SPI Mode (as Master). Read from Slave(another chip). Received SPI Data saved with DMA from Usci A1 in Memory. SPI Clock 400 kHz. It works.

Then I set SPI clock to 800 kHz and get Problem. Infinite loop in usci Tx ISR. I have ISR for DMA. With SPI Clock 400 kHz DMA ISR is called and all goes ok( Tx interrupt will be disabled), but with SPI Clock 800 kHz no DMA ISR will be called, althought I see DMAIFG =1(in Debug stop). Usci Tx ISR all the time in infinite loop and UCAxTXBUF will filled with 0x00 (to produce Clock for Slave Read).

Is anybody know, why DMA ISR not called with 800 kHz SPI Clock? (And called with SPI Clock 400 kHz) Is anybody has this Problem? Solution?

Regards

Alex